Composite Material (e.g., Fibers Or Strands Embedded In Solid Matrix) Patents (Class 257/746)
  • Patent number: 7932585
    Abstract: At least one film composite is laminated on a surface of at least one electrical component. The film composite includes at least one electrically-conducting plastic film with at least one electrically conducting conductor. The electrically-conducting plastic film has a high-ohmic resistance. This method may be used in planar large-surface electrical contacting technology for the production of modules with power semiconductors, where an electrical contacting of the components is achieved by the plastic films. A low lateral electrical conductivity is achieved, such that an electrical charging of the plastic films required for the contacting technology is prevented on operation of the component or the module.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: April 26, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventors: Laurence Amigues, Michael Kaspar, Herbert Schwarzbauer
  • Patent number: 7928566
    Abstract: Conductive bump (17) formed on a surface of electrode terminal (11) of an electronic component. Conductive bump (17) is composed of at least a plurality of cured resin materials having different conductive filler densities. Thus, a short circuit and a connection failure due to crush of conductive bump (17) at the time of mounting can be prevented.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Yagi, Daisuke Sakurai
  • Patent number: 7911057
    Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 22, 2011
    Assignee: NXP B.V.
    Inventor: Wayne Nunn
  • Publication number: 20110049714
    Abstract: The invention relates to an illuminant (40) comprising a standardised connection socket (42) and a cover (50) consisting of a light-permeable material defining an inner chamber (52). A light chip arrangement (10; 110) comprising at least one semiconductor structure (14; 114) is contacted between contact regions (48a, 48b) of at least two supply lines (44a, 44b).
    Type: Application
    Filed: October 11, 2007
    Publication date: March 3, 2011
    Applicant: NOCTRON SOPARFI S.A.
    Inventors: Georg Diamantidis, Frederic Tonhofer
  • Publication number: 20110042813
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Application
    Filed: January 9, 2009
    Publication date: February 24, 2011
    Applicants: VORBECK MATERIALS CORPORATION, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-hua Chen, Robert K. Prud'Homme
  • Patent number: 7884359
    Abstract: Described herein is a field ionization and electron impact ionization device consisting of carbon nanotubes with microfabricated integral gates that is capable of producing short pulses of ions.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: February 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David S. Y. Hsu, Jonathan L Shaw
  • Patent number: 7876596
    Abstract: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between an anode layer (12) and a cathode layer (16). Further, a hole injection transport layer (13) is provided between the switching layer (14) and the anode layer (12), and an electron injection transport layer (15), between the switching layer (14) and the cathode layer (16). An intermediate layer is provided between the switching layer and the adjacent layer. The radical polymer is preferably nitroxide radical polymer. The switching layer (14), the hole injection transport layer (13) and the electron injection transport layer (15) are formed by being stacked by a wet process.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: January 25, 2011
    Assignee: Waseda University
    Inventors: Hiroyuki Nishide, Kenji Honda, Yasunori Yonekuta, Takashi Kurata, Shigemoto Abe
  • Publication number: 20100327444
    Abstract: The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Daiyu Kondo, Taisuke Iwai, Yoshitaka Yamaguchi, Ikuo Soga
  • Publication number: 20100301479
    Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 2, 2010
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Haixin Yang, Roberto Irizarry, Patricia J. Olliver
  • Patent number: 7830001
    Abstract: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being positioned on at least a portion of a principal face 1a of the Cu base 1; and a first Sn—Cu-type alloy layer 3 covering the first principal face 2a and side faces 2c and 2d of the Mo base 2, the first Sn—Cu-type alloy layer 3 containing no less than 1 mass % and no more than 13 mass % of Sn.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: November 9, 2010
    Assignee: Neomax Materials Co., Ltd.
    Inventors: Masayuki Yokota, Kazuhiro Shiomi, Fumiaki Kikui, Masaaki Ishio
  • Patent number: 7830009
    Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Masataka Mizukoshi
  • Patent number: 7790600
    Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: September 7, 2010
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Pierre Jacobs, Bert Sels, Jasper Van Noyen, Caroline Whelan, Karen Maex, Filip de Clippel
  • Patent number: 7777335
    Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: August 17, 2010
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Motohiro Arifuku, Itsuo Watanabe, Kouji Motomura, Kouji Kobayashi, Yasushi Gotoh, Tohru Fujinawa
  • Publication number: 20100193952
    Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
    Type: Application
    Filed: April 14, 2009
    Publication date: August 5, 2010
    Inventors: Leonel Arana, Michael Newman, Devendra Natekar
  • Patent number: 7719112
    Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 18, 2010
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventor: Zheng John Shen
  • Patent number: 7709934
    Abstract: A package may include a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Xiang Yin Zeng, Jiangqi He, Guizhen Zheng
  • Patent number: 7705458
    Abstract: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Yongki Min
  • Publication number: 20100084757
    Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 8, 2010
    Inventors: Rajan Hariharan, James Hurley, Senthil Kanagavel, Jose Quinones, Martin Sobczak, Deborah Makita
  • Patent number: 7649266
    Abstract: For semiconductor chips (1) using thin film technology, an active layer sequence (20) is applied to a growth substrate (3), on which a reflective electrically conductive contact material layer (40) is then formed. The active layer sequence is patterned to form active layer stacks (2), and reflective electrically conductive contact material layer (40) is patterned to be located on each active layer stack (2). Then, a flexible, electrically conductive foil (6) is applied to the contact material layers as an auxiliary carrier layer, and the growth substrate is removed.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: January 19, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Andreas Ploessl, Stephan Kaiser, Volker Härle, Berthold Hahn
  • Publication number: 20090294966
    Abstract: A method of making an electrode, such as an interconnect for a semiconductor device, includes forming aligned carbon nanotubes using dielectrophoresis.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Applicants: UNIDYM, INC., DUKE UNIVERSITY
    Inventors: Jie Liu, Anna Fontcuberta I Morral
  • Patent number: 7622184
    Abstract: A stack of 50 layers of a first pitch-base carbon fiber sheet is formed, two sets of stack each having two second pitch-base carbon fiber sheets stacked therein are fabricated. At this time, the second carbon fiber sheets have a thermal expansion coefficient larger than that of the first carbon fiber sheet. Next, the stack of the first carbon fiber sheet is then held between two sets of stack of the second carbon fiber sheets. The stack of the first and second carbon fiber sheets are then impregnated with an epoxy-base resin composition and the resin is solidified. As a result a prepreg composed of the first and second carbon fiber sheets and the resin component composed of the epoxy-base resin composition is obtained. Thereafter, interconnections and the like are then formed on the prepreg, to thereby complete a multilevel interconnection board.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: November 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Mamoru Kurashina, Tomoyuki Abe
  • Patent number: 7615776
    Abstract: A method of assembling a circuit includes providing a template, enabling a semiconductor material to self assemble on the template, and enabling self-assembly of a connection between the semiconductor material and the template to form the circuit and a circuit created by self-assembly.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventor: Praveen Chaudhari
  • Patent number: 7612438
    Abstract: An active matrix substrate comprises a substrate, a plurality of adhesion parts provided on the substrate so as to have substantially the same height, and a plurality of active elements provided on the plurality of adhesion parts, respectively, each of the plurality of adhesion parts including a height control member and an adhesive.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Akiyama, Yujiro Hara, Yutaka Onozuka, Tsuyoshi Hioki, Mitsuo Nakajima
  • Publication number: 20090243103
    Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.
    Type: Application
    Filed: January 22, 2009
    Publication date: October 1, 2009
    Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Pierre Jacobs, Bert Sels, Jasper Van Noyen, Caroline Whelan, Karen Maex, Filip de Clippel
  • Patent number: 7582964
    Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: September 1, 2009
    Assignee: Kyocera America, Inc.
    Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
  • Publication number: 20090206483
    Abstract: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.
    Type: Application
    Filed: February 20, 2008
    Publication date: August 20, 2009
    Inventor: Kevin O'Brien
  • Patent number: 7550848
    Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: June 23, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7535014
    Abstract: A field ionization device can include a first insulator layer on a first side of a substrate, a conductive gate layer on the first insulator layer, a cavity in the substrate, a portion of first insulator over the cavity, an aperture in the portion of the first insulator layer and the conductive gate layer thereby forming an aperture and aperture sidewall. The device can include a second insulator layer on the aperture sidewall and surface of the cavity, a metallization layer over the second insulator layer, a catalyst layer on the metallization layer, and a carbon nanotube. The cavity can be made by etching a second side of the substrate to near the insulator layer, wherein the second side is opposite the first side. The carbon nanotube can be grown from the catalyst layer. The device can further include a collector located near the carbon nanotube. The conductive gate layer can be biased negative with respect to the carbon nanotube.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: May 19, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David S. Y. Hsu, Jonathan L. Show
  • Publication number: 20090051032
    Abstract: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric.
    Type: Application
    Filed: August 21, 2008
    Publication date: February 26, 2009
    Inventors: Brent M. SEGAL, Thomas RUECKES, Claude L. BERTIN
  • Patent number: 7485908
    Abstract: An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: February 3, 2009
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Abul F Anwar, Richard T. Webster
  • Patent number: 7456502
    Abstract: The invention provides a wiring board (2,15) to which a semiconductor chip (3) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board includes a connection electrode (14) that is formed on a bonding surface (2a, 15a) to which the semiconductor chip is to be bonded and that is used to make a connection with the semiconductor chip, an insulating film (6) that is formed on the bonding surface and that has an opening (6a) to expose the connection electrode, and a low-melting-point metallic part (16) that is provided on the connection electrode in the opening and that is made of a low-melting-point metallic material whose solidus temperature is lower than that of the connection electrode.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: November 25, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 7453157
    Abstract: A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: November 18, 2008
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
  • Patent number: 7439560
    Abstract: A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at least a part of the second region via an insulating layer. The semiconductor nanowire has a P-type semiconductor portion and an N-type semiconductor portion, and one of the P-type semiconductor portion and the N-type semiconductor portion is a common structural element of both the first and second regions.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 21, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Shioya, Sotomitsu Ikeda
  • Publication number: 20080246148
    Abstract: Integrated circuit devices include electrically conductive interconnects containing carbon nanotubes. An electrical interconnect includes a first metal region. A first electrically conductive barrier layer is provided on an upper surface of the first metal region and a second metal region is provided on the first electrically conductive barrier layer. The first electrically conductive barrier layer includes a material that inhibits out-diffusion of the first metal from the first metal region and the second metal region includes a catalytic metal therein. An electrically insulating layer having an opening therein is provided on the second metal region. A plurality of carbon nanotubes are provided as a vertical electrical interconnect in the opening.
    Type: Application
    Filed: January 10, 2008
    Publication date: October 9, 2008
    Inventors: Seokjun Won, Hokyu Kang
  • Publication number: 20080237858
    Abstract: An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the second insulating film on the conductive pattern, carbon nanotubes formed in the hole to extend from a surface of the conductive pattern, and a buried film buried in clearances among the carbon nanotubes in the hole.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Mizuhisa NIHEI
  • Patent number: 7429795
    Abstract: Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 30, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Tsai Su, Chin-Chi Shen, Ming-Jer Chiu, Chih-Chiang Chen
  • Publication number: 20080224279
    Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 18, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Terrence Caskey, Lawrence Douglas Andrews, Scott McGrath, Simon J.S. McElrea, Yong Du, Mark Scott
  • Publication number: 20080211095
    Abstract: A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive adhesive contains a conductive filler including silver (Ag); and the second conductive adhesive contains a conductive filler including a metal selected from a group consisting of tin (Sn), zinc (Zn), cobalt (Co), iron (Fe), palladium (Pd), and platinum (Pt).
    Type: Application
    Filed: February 27, 2008
    Publication date: September 4, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Motoyuki NISHIZAWA
  • Patent number: 7414313
    Abstract: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 19, 2008
    Assignee: Eastman Kodak Company
    Inventors: Debasis Majumdar, Glen C. Irvin, Jr., Charles C. Anderson, Gary S. Freedman, Robert J. Kress
  • Publication number: 20080191351
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080191350
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7405419
    Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Reza M. Golzarian, Robert P. Meagley, Seiichi Morimoto, Mansour Moinpour
  • Publication number: 20080169563
    Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.
    Type: Application
    Filed: September 14, 2007
    Publication date: July 17, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Awano, Masataka Mizukoshi
  • Publication number: 20080164612
    Abstract: A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns, a first resin that has a softening point between 80-260° C., solvent, curing agent, and a second resin, wherein at room temperature the first resin is substantially soluble in the solvent.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 10, 2008
    Inventor: Qizhuo Zhuo
  • Publication number: 20080122090
    Abstract: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 29, 2008
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Robert Tonti, Chih-Chao Yang
  • Patent number: 7348670
    Abstract: Cylinders having Al as a major constituent are orderly arrayed in an (Si, Ge) matrix. In a nanostructure in the form of a mixture film having a plurality of cylinders having Al as a major constituent, and a matrix region surrounding the plurality of cylinders and having Si and/or Ge as a major constituent, the total amount of Si and Ge is in the range from 20 to 70 atomic % in the mixture film, the cylinders are orderly arrayed, the diameter of the cylinders is in the range from 1 to 30 nm, and the interval between the cylinders is 30 nm or less.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: March 25, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tohru Den, Kazuhiko Fukutani
  • Patent number: 7332810
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 19, 2008
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Publication number: 20080029845
    Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 7, 2008
    Applicant: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION
    Inventor: Zheng John Shen
  • Patent number: 7298046
    Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 20, 2007
    Assignee: Kyocera America, Inc.
    Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
  • Patent number: 7247877
    Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Mark E. Masters, Leah M. P. Pastel, David P. Vallett