Abstract: The purpose of the invention is to provide a thermoelectric power generation body capable of generating power not only from solar heat and geothermal heat but also from a heat source of medium or low temperature which has been impossible to be utilized by the conventional art, with high thermal efficiency.

Abstract: A wire bonding pad of a semiconductor integrated circuit device includes a first, test portion to which a probe tip may be contacted, and a second, wire bonding portion to which a wire is bonded for electrically connecting the bonding pad to a carrier or lead frame. Providing a separate, test portion prevents the wire bonding portion from being damaged by a probe tip during testing.

Abstract: A small semiconductor device close in size to a semiconductor chip which prevents warping of semiconductor chips or wafer and delamination of an interface from an interlayer insulating film, both caused by thermal stresses of a rewiring layer. The use of a Cu composite alloy containing 80 vol. % or less of Cu2O, which alloy has a smaller linear thermal expansion coefficient and a smaller elastic modulus than those of pure copper, as a main material of the rewiring layer can reduce the thermal stresses in the rewiring layer, realizing a semiconductor device in which warping of semiconductor chips or wafer and delamination of layers will not easily occur.

Abstract: A semiconductor ceramic for thermistors contains zinc oxide and titanium oxide as main components and a predetermined content of manganese. Also, a chip-type thermistor including the semiconductor ceramic is provided. By adding manganese, the resistance-temperature characteristic is controllable in the range of positive temperature coefficient to negative temperature coefficient. Also, by adding nickel, the resistivity is controllable. As a result, a thermistor material which provides a series of semiconductor ceramics having various resistivities and various B constants in a low range, for example 0 to 1,000 K, is available.

Abstract: There is provided a semiconductor device including (a) a substrate, (b) a semiconductor chip mounted on the substrate, (c) a wall having a closed cross-section and mounted on the substrate such that the semiconductor chip is surrounded by the wall, and (d) a cover covering the wall therewith so that a closed cavity is defined by the substrate, the wall and the cover, the cavity being designed to be under a pressure almost equal to an atmospheric pressure at a temperature highest in both steps of fabricating the semiconductor device and steps expectable after the semiconductor device is completed. The semiconductor device can prevent defectiveness such as electric leakage and electromigration, and further prevent occurrence of “popcorn” phenomenon which might occur in an annealing step.

Abstract: A circuit board and a ball grid array (BGA) package having a solder joint with improved reliability are disclosed. The circuit board has a chip mounting surface in which wiring patterns are formed and a solder ball mounting surface in which a plurality of solder balls are mounted and electrically interconnected to the wiring patterns. The circuit board comprises a plurality of ball lands connected to the solder balls. The circuit board further includes solder ball opening area defined by a solder ball mask on the solder ball mounting surface and exposing the ball land from the solder ball mask, a plurality of pattern connecting portions each connected to corresponding one of the ball lands, and conductive wiring patterns linked together with the pattern connecting portions and electrically interconnected to the solder balls. The plurality of pattern connecting portions are aligned radially inwardly toward substantially a center point of the solder ball mounting surface.

Abstract: A semiconductor chip is mounted in face-up disposition, with a contact-bearing front surface facing away from a substrate such as a circuit panel, and with a rear face facing toward the substrate. A backing element having terminals is disposed between the rear face of the chip and the substrate, and the terminals of the backing element are connected to contact pads on the substrate. The terminals of the backing element are movable with respect to the chip to compensate for differential thermal expansion of the chip and substrate.

Abstract: A semiconductor ceramic having a negative temperature coefficient of resistance, the element comprising about 0.1 to 20 mol % of AMnO3 (A represents at least one of Ca, Sr, Ba, La, Pr, Nd, Sm, Eu, Gd, Th, Dy and Ho) and to a spinel composite oxide made of a solid solution of Mn and at least one element in Ti, V, Cr, Fe, Co, Ni, Cu, Zn, Mg and Al. As a perovskite Mn composite oxide, one or more of CaMnO3, SrMnO3, BaMnO3, LaMnO3, PrMnO3, NdMnO3, SmMnO3, EuMnO3, GdMnO3, TbMnO3, DyMnO3 and HoMnO3 may be used.

Abstract: A multilayer board free from breakage at connecting parts due to thermal fatigue is provided. A multilayer board 1 of the present invention comprises alternating polyimide films 11-16 and copper films 21-26. The polyimide films 11-16 have a thermal expansion coefficient of 2-5 ppm/° C. so that the multilayer board 1 has a total thermal expansion coefficient of less than 10 ppm/° C. Because of the thermal expansion coefficient close to that of the semiconductor element to be mounted, no breakage occurs at connecting parts to the semiconductor element. The multilayer board 1 of the present invention may be used as both interposer and motherboard.

Abstract: A center bond flip-chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a layer of conductive material and a layer of elastomeric material. At least one pocket is formed in the layer of elastomeric material and sized and shaped to house a solder ball. The solder ball is electrically connected to a die positioned on the layer of elastomeric material and also electrically connected to the layer of conductive material.

Abstract: An electronic package comprising a semiconductor chip mounted on a substrate is formed by bonding a structure which covers at least an outer surface of the semiconductor chip and has the same or about the same thermal expansion coefficient as the substrate to the semiconductor chip's side surface of the substrate. This reduces warp and deformation caused by temperature changes during package operation.

Abstract: An active microelectronic element such as a semiconductor chip or wafer is bonded to an interconnect element having substantially the same coefficient of thermal expansion as the active element using small, rigid bonds, desirably made by a solid-phase bonding technique, which accommodate numerous closely-spaced interconnections. The assembly is provided with terminals movable with respect to the active element and interconnect element. The interconnect element desirably provides low-impedance conductive paths interconnecting active electronic devices within the active element.

Abstract: A moldless semiconductor device comprising a semiconductor chip held between outer-connecting terminals and connected electrically to the terminals is provided. At least one of the two terminals has, at its region contiguous to the semiconductor chip or at its region contiguous to the semiconductor chip and a region vicinal thereto, a hardness different from all other regions of the one terminal. This moldless semiconductor device can withstand significant external force and exhibits high reliability when used in photovoltaic device modules.

Abstract: A contact clip for the aluminum contact of a semiconductor device has a central nickel-iron body, preferably Nilo alloy 42, which is coated on top and bottom by a soft, but high conductivity metal such as gold, silver or copper. The nickel-iron body has a thickness of about 15 mils, and is about the thickness of the silicon die. The conductive layers have a thickness of about 5% to 20% of that of the nickel-iron core.

Abstract: A wafer-level method for mass production of surface-mounting, chip-size (“CS”) ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) semiconductor packages includes the wire-bond or flip-chip attachment of ceramic substrates to the active surface of corresponding chips while they are still integral to a semiconductor wafer, thereby reducing manufacturing costs of the packages relative to that of individually packaged chips. The substrates have a thermal coefficient of expansion (TCE) closely matching that of the underlying chip.

Abstract: External connection electrodes can be positively mounted on a substrate when the pitch between the external connection electrodes is reduced and the diameter of each through hole formed in the substrate is reduced. A semiconductor chip is mounted on a first surface of a tape substrate. Electrode films are formed on the first surface of the tape substrate, each of the electrode films electrically connected to the semiconductor chip. External connection electrodes are provided on a second surface of the tape substrate, each of the external connection electrodes connected to a respective one of the electrode films via a through hole formed in the tape substrate. The external connection electrodes are formed on the electrode films by plating. A diameter S1 of a portion of each of the external connection electrodes protruding from the second surface of the tape substrate and a diameter S2 of the through hole satisfy a relationship S1≦S2.

Abstract: A stable, reliable ohmic contact, and improved semiconductor articles and opto-electronic circuits incorporating same, are disclosed. According to an illustrative embodiment of the invention, an ohmic contact having a plurality of thermodynamically-stable layers and layer interfaces is formed by providing a structure comprising multiple, appropriately-thick and specifically-organized layers of suitably-selected material, and exposing the structure to heat to cause reaction to take place between the various layers. Due to the thermodynamic stability of the resulting reacted layers and the interfaces between such layers, there is substantially no tendency for further reaction to occur within the ohmic contact.

Abstract: An object is to obtain long-term reliability of an electric connection in a power semiconductor module. In a power semiconductor module, the main circuit interconnection directly connected to a power semiconductor chip (3) is formed of a busbar (6) and the power semiconductor chip (3) and the busbar electrode (6a) of the busbar (6) are electrically connected through a conductive resin (12). A member (13) having lower thermal expansion than the busbar electrode (6a) is joined to the busbar electrode (6a) in the part adjacent to said power semiconductor chip (3).

Abstract: A low-cost integrated circuit package is provided for packaging integrated circuits. In preferred embodiments, the package comprises a flexible circuit that is laminated to a stiffener using a dielectric adhesive, with the conductive traces on the flexible circuit facing toward the stiffener but separated therefrom by the adhesive. The conductive traces include an array of flip-chip attachment pads. A window is formed in the stiffener over the attachment pad array, such as by etching. The adhesive is then removed over the attachment pads by laser ablation, but left in place between the pads, thus forming a flip-chip attachment site. In preferred embodiments, this invention eliminates the need for high-resolution patterned adhesive, and it also eliminates the need for application of a solder mask at the flip-chip attachment site, because the remaining adhesive performs the solder mask function of preventing bridging between attachment pads.

Abstract: An embodiment of the invention includes an integrated circuit package having a substrate, an integrated circuit mounted to the substrate, a thermal element, and a heat pipe disposed between the integrated circuit and the thermal element. The heat pipe includes a retaining structure impregnated with a thermal grease. The heat pipe is a result of a process that includes the step of impregnating the retaining structure with a thermal grease prior to disposing the heat pipe between the integrated circuit and the thermal element.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a metal sheet, such as a copper sheet, and a thermally conductive insulating layer, such as a thermally conductive polyimide material, to which is also bonded a layer of a b-stage adhesive material. The ground plane assembly may be bonded to the lead frame by placing the b-stage adhesive layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage adhesive layer to the lead frame without oxidizing the lead frame.

Abstract: A contactor system is adapted for use when testing a ball grid array (BGA) device, and includes a conductive socket that is retained on a testing board and that establishes a ground connection therewith. The socket is formed with a receiving space adapted for receiving the BGA device therein. An insulating guide unit is mounted on the socket in the receiving space and is adapted to guide loading movement of the BGA device into the receiving space via an open top section of the latter and to prevent undesired electrical contact between the socket and the BGA device. A surface mount matrix is disposed on top of the testing board and is clamped between the socket and the testing board. The surface mount matrix is accessible via an open bottom section of the receiving space, and is adapted to contact solder balls on the BGA device directly so as to establish electrical connection between the BGA device and testing circuit layout on the testing board.

Abstract: An electronic device includes an integrated circuit chip, an interposer and a printed circuit board. A first ball connector is used to connect the interposer to printed circuit board. The interposer may be connected to the integrated circuit chip by a second ball connector or a wire bond. The first ball connector is disposed on a cantilever structure formed in the interposer. The cantilever is formed by creating a channel in the interposer. The cantilever absorbs stress caused by a difference between the thermal expansion of the integrated circuit chip as compared to the printed circuit board. The cantilever thus reduces stress in the ball connector by allowing the ball connector to move within a plane defined by the interposer.

Abstract: An electronic device that is equipped with a plurality of bonding pads positioned on the device for making electrical interconnections and electrically conductive composite bumps adhered to the bonding pads wherein the bumps are formed of a composite material consisting of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles based on the total volume of the metal particles and the thermoplastic polymer. The present invention is also directed to a method of making electrical interconnections to an electronic device by pressing a plurality of composite bumps of a polymeric based material against a substrate having an electrically conductive surface by mechanical means under a sufficient temperature and/or a sufficient pressure.

Abstract: A circuit board has traces attached to a flexible trace surface such that the traces can be displaced in a direction of thermal expansion of a component attached to the traces without causing the failure of the solder joint between the component and the trace. In one embodiment, the printed circuit board substrate is etched away in areas not covered by the traces such that flexible protuberances are formed from the substrate underneath the traces. In one method for constructing such a circuit board, a conductive layer is deposited on the printed circuit board substrate. The conductive layer is then etched to form conductive traces. The printed circuit board substrate is then selectively etched using the traces as a mask for etching the printed circuit board substrate. In a second printed circuit board embodiment, a flexible layer of a material is deposited onto the printed circuit board substrate. The traces are then formed on top of the flexible layer.

Abstract: A method and encapsulation material for encapsulating the solder joints of an IC device mounted on the substrate of an electronic circuit assembly. The encapsulation material is formulated to be sufficiently opaque to x-radiation to enable the use of x-radiation imaging techniques to detect air pockets and voids in the encapsulation material that might degrade the fatigue life properties of the solder joints encapsulated by the encapsulation material. For the purpose of enhancing the fatigue life properties of the solder joints, the encapsulation material contains a filler material dispersed in a polymeric material, such as an epoxy, such that the encapsulation material is characterized by a coefficient of thermal expansion approximately equal to that of the solder joints. The filler material contains a sufficient amount of an element to render the encapsulation material opaque to x-radiation.

Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

Abstract: The mounting structure of an electronic component having bumps includes a multi-layer substrate provided with an outermost layer substrate having electrode on the top thereof and a lower layer substrate comprising at least one layer substrate joining the bottom of the outermost layer substrate, an electronic component having bumps bonded with the electrodes formed on the top of the outermost layer substrate for connecting the electronic component and the substrate, and under-fill resin formed between the electronic component and the outermost layer substrate, in which the coefficient of linear thermal expansion of the under-fill resin is larger than that of the electronic component, but smaller than that of the outermost layer substrate.

Abstract: A device having a thin film and/or a solder ball formed on a substrate. The thin film and the solder ball each include a metal and a compound that includes an oxide, nitride, or carbide precipitate of an expandable element or a contractible element. The compound is distributed in the metal to control the tensile and compressive stresses and mechanical properties of the thin film and the solder ball.

Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each of the semiconductor modules includes a plurality of switching device chips and at least one diode chip formed on a metal substrate. Electrode plates are provided in locations of the module adjacent to the switching device chips and the diode chips to facilitate connection of the electrodes of the respective chips to one another and to the outside of the module.

Abstract: A substrate for connecting one element having a first coefficient of thermal expansion to another element having a differing coefficient of thermal expansion that will alleviate interconnection problems due to thermal mismatch.

Abstract: An electronic device that is equipped with a plurality of bonding pads positioned on the device for making electrical interconnections and electrically conductive composite bumps adhered to the bonding pads wherein the bumps are formed of a composite material consisting of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles based on the total volume of the metal particles and the thermoplastic polymer. The present invention is also directed to a method of making electrical interconnections to an electronic device by pressing a plurality of composite bumps of a polymeric based material against a substrate having an electrically conductive surface by mechanical means under a sufficient temperature and/or a sufficient pressure.

Abstract: A heat spreader for a semiconductor device is constituted by an integral laminate of alternatingly stacked and diffusion-bonded Fe-Ni alloy sheets and copper-group metal sheets, the laminate having a one-directional stripe pattern of the Fe-Ni alloy sheets and the copper-group metal sheets, which appears on a planar surface on which a silicon chip is disposed. It is produced by (a) alternatingly stacking Fe-Ni alloy sheets and copper-group metal sheets, (b) hot isostatic-pressing the resulting stack of the metal sheets to form a slab, (c) rolling the slab vertically to the laminating direction of the metal sheets to form an integrated stripe-pattern laminate, and (d) cutting the integrated stripe-pattern laminate to a predetermined shape.

Abstract: A material for a semiconductor substrate comprising an aluminum-silicon alloy containing from 50% to 80% by weight of silicon and having a thermal conductivity of 0.28 cal/cm.sec..degree. C. or higher, a coefficient of thermal expansion of 12.times.10.sup.-6 /.degree. C. or smaller and a density of 2.5 g/cm.sup.3 or lower. This material is produced by molding an Al--Si alloy powder, which has been obtained through rapid solidification by atomization, to form a compact and then consolidating the compact by means of forging, sintering, etc. The substrate material may have an Al or Al alloy covering layer at least one surface thereof and, further, as necessary, an insulating or plating layer on the covering layer. The thus obtained substrate material is lightweight and has a suitable coefficient of thermal expansion for a substrate as well as a high thermal conductivity. Therefore, a semiconductor device with high performance and reliability can be obtained using such substrate material.

Abstract: This high-power semiconductor device comprises (a) a disk of refractory metal having flat faces at its opposite sides and (b) two wafers of a semiconductor material having a coefficient of expansion similar to that of the refractory metal, the wafers being alloyed to the faces of the refractory metal disk in substantially aligned relationship to each other to form an assembly of the wafer and the disk with alloyed joints between the wafers and the disk.

Abstract: The present invention includes an integral copper column with a solder bump flip chip. An integrated circuit chip is provided having an electrical circuit and including at least two contact pads. A thin layer of barrier metallization is provided over the contact pads. A support substrate is provided having a circuit layer with raised features that include copper traces. A solder bump connects the contact pad on the integrated circuit chip and the raised features of the flex circuit to provide an integral copper column with a solder bump flip chip.

Abstract: A thermal interface 26 between a heat source (e.g., an IC die) 24 and a heat sink 28 comprises a metallic mesh (26a) filled with a thermally conductive semi-liquid substance (26b). The thermally conductive semi-liquid substance may comprise, e.g., silicone grease or paraffin. The wire mesh may comprise silver, copper and/or gold cloth.

Abstract: A power module has a metallic base plate layer and a substrate layer that has a first metallic layer, a dielectric layer, and a second metallic layer. A solder layer thermally and electrically connects the second metallic layer to the base plate. A plurality of silicon dice are mounted to the first metallic layer of the substrate. The solder layer has a void development region which after a predetermined number of thermal cycles does not significantly increase. The silicon dice are oriented on the substrate layer so that the silicon dice are not aligned over the void development region corresponding to the useful life of the module. The metallic base plate may also be mounted to a heatsink through a thermal grease layer. The heatsink may comprise the outer covering of the power module.

Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A packaging system for minimizing thermal-induced stress in a high power semiconductor device. The system is comprised of an electrically insulating, thermally conductive substrate having planar upper and lower surfaces, a semiconductor die having a planar lower heat extraction surface attached to said upper surface of said substrate, and electrically insulating thermal compound disposed between and in contact with the said lower heat extraction surface of said substrate and the system heat extraction upper surface. .DELTA.L.varies..DELTA.S is defined in Equation 12, wherein T.sub.B is the temperature at said outer edge of the lower heat extraction surface of said die, T.sub.D is the temperature at said outer edge of the lower surface of said substrate, and PPM is part per million.

Abstract: A high resolution optical coupling device includes optical coupling material bonded to a CCD wafer surface and a fiber optic bundle. The CCD wafer is bonded to a substrate, and a thermal compensation plate is bonded to an opposite face thereof to compensate effects of differential thermal contraction and expansion of the CCD wafer and substrate. Substrate-adjusting elements engage the substrate to shape the CCD wafer surface to match a mating surface of a fiber optic bundle before the thermal compensation plate is attached to the substrate. A null fringe pattern of an interferometer indicates when a perfect match is achieved. A thin layer of optical coupling material then is used to bond the CCD surface to the matching surface of the optic fiber bundle. Thermal compensation material can be included in a rigid hermetic seal structure between the substrate and the fiber optic bundle to reduce bonding interface shear stress in the optical coupling material due to volume changes thereof during thermal cycling.

Abstract: An integrated circuit chip die (12) is manufactured with sacrificial structures (16) placed at the areas of die that are likely to experience cracks. According to one embodiment of the invention, these sacrificial structures are placed at the corners of the die. The sacrificial structures are constructed with metal lines (22, 24) that resist propagation of cracks into the area of the die containing electronic devices. The metal lines form lattice steps so that the surface of the die will more tightly bond to the molding compound that makes up the die package.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a metal sheet, such as a copper sheet, and a thermally conductive insulating layer, such as a thermally conductive polyimide material, to which is also bonded a layer of a b-stage adhesive material. The ground plane assembly may be bonded to the lead frame by placing the b-stage adhesive layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage adhesive layer to the lead frame without oxidizing the lead frame.

Abstract: An integrated circuit package, and integrated circuit assembly having such a package, includes a base portion and a cover portion which cooperatively enclose an integrated circuit chip. The base and cover portions are formed of composite material and have matching coefficients of thermal expansion. Because the base and cover portions each match the other's thermal expansions and contractions, no stresses are generated in the package from heating and cooling during and following operation of the integrated circuit chip, and no such thermally produced physical stresses are transferred to the circuit chip to shorten its life. A version of the package includes plural lamina, and may include facial metallic coating layers on the lamina for shielding, electromagnetic shielding, and electrical interconnection of the integrated circuit chip. Another version of the package utilizes the facial metallic coating layers to join portions of the package by soldering.

Abstract: This invention includes semiconductor devices including the heat sink with a slitted metal strip, such as copper, which is coiled or folded to produce an array of flexible flat fingers for mechanical, thermal and electrical contact with the silicon die, such as a power transistor. The use of a slitted metal strip instead of a bundle of wires makes fabrication of the flexible mount simpler and more economical. The flexible flat fingers are able to accommodate hot spots on the semiconductor device and change in thermal gradients as the device is operated.

Abstract: A power semiconductor component includes a semiconductor body having anode and cathode sides and a given thermal coefficient of expansion. Contact electrodes are each disposed on a respective one of the anode and cathode sides and are made of a metal having a thermal coefficient of expansion differing from the given thermal coefficient of expansion. At least two contact surfaces are disposed one above the other under pressure, between the semiconductor body and the contact electrodes. At least one of the contact surfaces has a layer formed of an amorphous carbon-metal compound.

Abstract: A hybrid integrated circuit of the invention is formed of an insulation substrate, a thick film conductor printed and sintered on the insulation substrate, and a terminal conductor and a circuit part connected to the first thick film conductor. A first electrically conductive metal plate is brazed on the first thick film conductor and connects the circuit part and the first terminal. Electric current between the circuit part and the first terminal mostly flows through the metal plate.

Abstract: A semiconductor-mounting heat-sink base for use with a plastic package or flexible printed wiring board which eliminates the possibility of semiconductor or package reliability being adversely affected due to a difference in thermal expansion coefficient between the heat sink base and the semiconductor or plastic package. The heat-sink base has a semiconductor-mounting portion comprising a Cu--W or Cu--Mo composite alloy containing 5 to 25 wt. % of copper made by an infiltration process, and a portion adjacent to a plastic package which comprises a copper or copper alloy containing not less than 95% of copper.

Abstract: A plastic leaded semiconductor package (20) has a semiconductor device (614) encapsulated in the package and mounted to a lead frame (612). The lead frame has a plurality of leads (622) that extend beyond the body (610) of the encapsulated package. Each of the plurality of leads is made from a metal having a predetermined coefficient of thermal expansion. A second metal (627) with a different coefficient of thermal expansion is disposed on at least one portion of each of the leads.

Abstract: A multilayer conductive wire is formed of a plurality of conductive layers stacked upon each other, and has a slit shaped groove extending in the direction intersecting the direction of stress in at least one conductive layer. With the groove mating with a protrusion in another conductive layer or a protrusion in an insulating film layer, a sliding phenomenon between the layers due to the stress can be restrained, so that a multilayer conductive wire free from destruction due to the sliding phenomenon caused by the stress and without losing conductivity can be provided.