Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphene layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

Abstract: A tungsten film forming method in which a substrate having a TiN film formed thereon is disposed in a processing container and a tungsten film is formed above a surface of the substrate while heating the substrate in a reduced pressure atmosphere, includes forming a first film of an aluminum-containing material on the substrate and forming the tungsten film on the first film.

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Abstract: Embodiments relate to an integrated process for forming an elastomeric layer over an epitaxial structure of multiple light emitting diode (LED) dies, and then etching the elastomeric layer into individual elastomeric interface layers (elayers) on each of the LED dies and etching the epitaxial structure to singulate the LED dies. The elayer allows each LED die to be picked up by a pick-up head (or pick and place head (PPH)), and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (uLED) dies.

Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

Abstract: A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.

Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is over the first dielectric layer. A compound recess is in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature.

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Abstract: The present disclosure relates to a method for producing a network of interconnected nanostructures comprising the steps of: providing a substantially plane substrate; growing a plurality of elongated nanostructures from the substrate; kinking the growth direction of at least a part of the nanostructures such that at least part of the kinked nanostructures are growing in a network plane parallel to the substrate, and creating one or more network(s) of interconnected kinked nanostructures in the network plane, wherein a dielectric support layer is provided below the network plane to support said network(s) of interconnected nanostructures.

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

Abstract: An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (CTE).

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

Abstract: A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.

Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.

Abstract: A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer.

Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.

Abstract: A semiconductor power device may include a Silicon Carbide (SiC) layer having an active power device formed on a first surface thereof. An Ohmic contact layer may be formed on a second, opposing surface of the SiC layer, the Ohmic contact layer including Nickel Silicide (NiSix) with a first silicide region containing a first precipitate of non-reacted carbon disposed between the SiC layer and a second silicide region. The second silicide region may be disposed between the first silicide region and a third silicide region, and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of non-reacted carbon. The third silicide region may contain a second precipitate of refractory metal carbide. A solder metal layer may be formed on the Ohmic contact layer, with the third silicide region disposed between the second silicide region and the solder metal layer.

Abstract: This invention relates to a platinum electrodeposition bath which is capable of forming platinum deposits having an attractive shiny granular surface like a velvet, which is particularly useful in jewelry manufacturing. The velvet effect can be illustrated by comparing the surface roughness with a bright smooth platinum deposit.

Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.

Abstract: In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first transistor includes a first control terminal on a top side of the insulating layer, a first source terminal on the top side of the insulating layer, and a first drain terminal on a bottom side of the insulating layer. The circuit package includes a second transistor extending through the insulating layer, where the second transistor includes a second control terminal on the top side of the insulating layer, a second source terminal on the bottom side of the insulating layer, and a second drain terminal on the top side of the insulating layer.

Abstract: A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the carbon, heat treatment is performed on the carbon to turn the carbon into graphenes which are stacked in a plurality of layers, and the catalytic material and a part of the graphenes on the insulating film are removed to make the graphenes remain only in the trench.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may comprise depositing metal layers, such layers of a transition metal, over a conductive substrate. Dopant layers may subsequently be deposited on the layers of the transition metal, followed by annealing of the layers of transition metal and dopant layers. Responsive to annealing, dopant from the dopant layers may diffuse into the one or more layers of transition metal, thereby forming a CEM.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.

Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.

Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.

Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

Abstract: To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.

Abstract: A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.

Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the carbon, heat treatment is performed on the carbon to turn the carbon into graphenes which are stacked in a plurality of layers, and the catalytic material and a part of the graphenes on the insulating film are removed to make the graphenes remain only in the trench.

Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.

Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.

Abstract: Provided herein are methods for selectively forming layers of metal films on one portion of a substrate while leaving adjacent portions of the substrate uncoated. The methods provide for selectively depositing metal films on a conductive surface, such as ruthenium oxide, disposed on or near an insulating portion of the substrate, such as a silicon dioxide (SiO2) surface. The invention provides methods to simultaneously contact the substrate surface with both the precursor gas and the inhibitor agent leading to the selective formation of metal nuclei on the conductive portion of the substrate. In the methods described, nuclei are selectively formed by a disproportionation reaction occurring on the conductive portion of the substrate but not on the insulating portion of the substrate.

Abstract: A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.

Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.