Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 9946676
    Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that ?k/n? hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Gerald S. Pasdast, Mark S. Birrittella, Ishwar Agarwal, Lip Khoon Teh, Su Wei Lim, Anoop Kumar Upadhyay
  • Patent number: 9947627
    Abstract: A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 9941135
    Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sejun Park, Dohyung Kim, Jaihyung Won, Sangho Roh, Eunsol Shin, Seung Moo Lee, Gyuwan Choi
  • Patent number: 9940957
    Abstract: A conductor trace is formed on a base insulating layer. The conductor trace includes two terminal portions and one wiring portion. The wiring portion is formed to connect the two terminal portions to each other and extend from each terminal portion. A metal cover layer is formed to cover the terminal portion and the wiring portion of the conductor trace and continuously extend from a surface of the terminal portion to a surface of the wiring portion. The metal cover layer is made of metal having magnetism lower than magnetism of nickel, and is made of gold, for example. A cover insulating layer is formed on the base insulating layer to cover a portion, of the metal cover layer formed on the conductor trace, covering the wiring portion and not to cover a portion of the metal cover layer covering the terminal portion.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 10, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Daisuke Yamauchi, Hiroyuki Tanabe
  • Patent number: 9935076
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 3, 2018
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Patent number: 9922970
    Abstract: An apparatus includes a substrate and an interposer associated with the substrate. The apparatus further includes a first device disposed within the substrate or within the interposer and a second device disposed within the interposer. The first device and the second device are arranged in a stacked configuration.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Miguel Angel Miranda Corbalan
  • Patent number: 9911693
    Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
  • Patent number: 9911766
    Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate an array substrate, which can avoid poor displays due to large coupling capacitance between a data line and a pixel electrode in an array substrate in the prior art. The manufacturing method comprises the following steps: S1, forming a data line metal layer on a substrate, and forming a pattern of a data line by a patterning process; S2, forming a semiconductor layer on the substrate formed with the data line thereon, and forming a pattern of an active layer by a patterning process, wherein the data line is connected with the active layer.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yong Chen, Zailong Mo, Tianlei Shi, Seungyik Park
  • Patent number: 9905739
    Abstract: A semiconductor light emitting device may include a light emitting package. A light emitting package may include a light emitting stack including a sequential stack of a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. An encapsulation layer may at least partially surround the second conductivity type semiconductor layer, and a wavelength conversion layer may cover the first conductivity type semiconductor layer. One or more of the encapsulation layer and the wavelength conversion layer may have a greater coefficient of thermal expansion (CTE) than a GaN-based compound semiconductor. The semiconductor light emitting device may include a stress applying structure that may apply a tensile stress to the light emitting stack. The light emitting stack may have reduced thermal droop at an operation temperature and improved luminous efficiency.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-wook Chung, Jung-jin Kim, Pun-jae Choi, Si-han Kim, Sung-don Gang, Ah-young Woo
  • Patent number: 9893009
    Abstract: In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Yu Chen, Chi-Yeh Yu, Chung-Hsing Wang
  • Patent number: 9887127
    Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas Vincent Licausi, Guillaume Bouche
  • Patent number: 9887203
    Abstract: A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 9871228
    Abstract: The present application relates to an organic light emitting device including a flexible substrate, and a preparing method thereof, and the method includes: 1) forming a polyimide layer on a carrier substrate; 2) forming a plastic substrate on the carrier substrate and the polyimide layer; 3) forming an organic light emitting device on the plastic substrate; and 4) separating the carrier substrate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 16, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jung Hyoung Lee, Junrye Choi, Jihee Kim
  • Patent number: 9870931
    Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chin-Sheng Wang, Shih-Hao Sun
  • Patent number: 9865601
    Abstract: The present disclosure relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a substrate, a first transistor and a first patterned conductive layer. The first transistor has a source region, a drain region in the substrate and a gate region on the substrate. The first patterned conductive layer is electrically connected to the drain region of the first transistor. The first patterned conductive layer includes a first section, a second section and a fusible device.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kai-Chun Lin, Yu-Der Chih, Chia-Fu Lee
  • Patent number: 9859321
    Abstract: A stack-type semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower interconnection on the lower substrate, a lower pad on the lower interconnection, and a lower interlayer insulating layer covering side surfaces of the lower interconnection and the lower pad. The upper device includes an upper substrate, an upper interconnection under the upper substrate, an upper pad under the upper interconnection, and an upper interlayer insulating layer covering side surfaces of the upper interconnection and the upper pad. Each of the pads has a thick portion and a thin portion. The thin portions of the pads are bonded to each other, the thick portion of the lower pad contacts the bottom of the upper interlayer insulating layer, and the thick portion of the upper pad contacts the top of the lower interlayer insulating layer.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghyun Kim, Doowon Kwon
  • Patent number: 9859236
    Abstract: Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Meng Meng Chong, Xuesong Rao, Chim Seng Seet, Xiaohua Zhan
  • Patent number: 9851257
    Abstract: The present disclosure is a infrared sensor capable of being integrated into a IR focal plane array. It includes of a CMOS based readout circuit with preamplification, noise filtering, and row/column address control. Using either a microbolometer device structure with either a thermal sensing element of vanadium oxide or amorphous silicon, a nanocomposite is fabricated on top of either of these materials comprising aligned or unaligned carbon nanotube films with IR trans missive layer of silicon nitride followed by one to five monolayers of graphene. These layers are connected in series minimizing the noise sources and enhancing the NEDT of each film. The resulting IR sensor is capable of NEDT of less than 1 mK. The wavelength response is from 2 to 12 microns. The approach is low cost using a process that takes advantage of the economies of scale of wafer level CMOS.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Magnolia Optical Technologies, Inc.
    Inventors: Ashok K. Sood, Elwood J. Egerton
  • Patent number: 9852991
    Abstract: A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric layer to expose a portion of the surface of the semiconductor substrate, forming a metal layer to fill up the opening, and removing the portion of the metal layer formed above the top surface of the dielectric layer by polishing. A metal oxide layer is formed on the surface of the metal layer after polishing. The method further includes removing the metal oxide layer from the top surface of the metal layer, forming a metal barrier layer on the top surface of the metal layer after the removal of the metal oxide layer to provide a more uniform thickness and a denser texture, and converting the metal barrier layer to a metal cap layer by introducing a silicon-containing gas onto a surface of the metal barrier layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 26, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jiquan Liu, Ming Zhou, Charles Wang
  • Patent number: 9825119
    Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Max G. Levy, Gary L. Milo, David C. Thomas
  • Patent number: 9818690
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9804468
    Abstract: A liquid crystal display includes: a gate line including a gate electrode; a data line including a source electrode; a drain electrode; an organic layer on the gate and data lines and the drain electrode, and a first opening defined therein; a first electrode on the organic layer, and a second opening defined therein; and a passivation layer on the first electrode, and a contact hole defined therein exposing the drain electrode. An interval taken in a first direction between a first edge of the gate electrode, the first edge parallel to a second direction in which the gate line is extended and which is different than the first direction, and a second edge of the first electrode second opening, the second edge parallel to the second direction and adjacent to the gate electrode first edge is 0 micrometer to about 6 micrometers.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hyun Park, Woong Ki Jeon, Sung In Ro, Dong Gun Oh
  • Patent number: 9799452
    Abstract: A ceramic electronic component includes a rectangular or substantially rectangular parallelepiped-shaped stack in which a ceramic layer and an internal electrode are alternately stacked and an external electrode provided on a portion of a surface of the stack and electrically connected to the internal electrode. The external electrode includes an inner external electrode covering a portion of the surface of the stack and including a mixture of a resin component and a metal component and an outer external electrode covering the inner external electrode and including a metal component. The inner external electrode includes a plurality of holes. An average opening diameter of the plurality of holes is not greater than about 2.5 ?m. Some or all of the plurality of holes are embedded with the metal component of the outer external electrode.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 24, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Hamanaka, Kota Zenzai, Taku Dekura, Kiyotaka Maegawa
  • Patent number: 9799654
    Abstract: A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole layer of opposite polarity relative to the polarity of the fin and reduces source to drain leakage. A semiconductor structure may include a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 9795026
    Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Nayandeep K. Mahanta, Joshua D. Heppner, Adel A. Elsherbini
  • Patent number: 9773834
    Abstract: A method of manufacturing a CMOS image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 26, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Wenjie Peng, Minwei Xi
  • Patent number: 9773698
    Abstract: An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids. A method may include depositing a filling material including a silicon-based resin having a molecular weight of less than about 30,000 Da and a porogen having a molecular weight greater than about 400 Da onto a structure comprising a patterned metal. The deposited filling material may be subjected to a first thermal treatment to substantially fill all gaps, and subjected to a second thermal treatment and a UV radiation treatment.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Geraud J. Dubois, Gregory Fritz, Teddie P. Magbitang, Hiroyuki Miyazoe, Willi Volksen
  • Patent number: 9754892
    Abstract: Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 5, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee
  • Patent number: 9756732
    Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 5, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Yasuaki Seki, Tomoyuki Nagata, Mitsuaki Toda
  • Patent number: 9748093
    Abstract: Aspects of the disclosure pertain to methods of forming conformal liners on patterned substrates having high height-to-width aspect ratio gaps. Layers formed according to embodiments outlined herein have been found to inhibit diffusion and electrical leakage across the conformal liners. The liners may comprise nitrogen and be described as nitride layers according to embodiments. The conformal liners may comprise silicon and nitrogen and may consist of silicon and nitrogen in embodiments. Methods described herein may comprise introducing a silicon-containing precursor and a nitrogen-containing precursor into a substrate processing region and concurrently applying a pulsed plasma power capacitively to the substrate processing region to form the conformal layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 29, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Patrick James Reilly, David Alan Bethke, Mihaela Balseanu
  • Patent number: 9741602
    Abstract: A semiconductor device is disclosed that comprises a first non-volatile memory cell, a second non-volatile memory cell, an active region between the first and second memory cells, and an electrically conductive contact touching the active region, wherein the contact has a horizontal cross-section that is at least five percent smaller in a first dimension than in a second dimension.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 22, 2017
    Assignee: NXP USA, INC.
    Inventors: Gong Chen, Linghui Wu
  • Patent number: 9741812
    Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Patent number: 9735392
    Abstract: A method of preparing a surface for deposition of a thin film thereon, wherein the surface including a plurality of protrusions extending therefrom and having shadowed regions, includes locally treating at least one of the protrusions.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: August 15, 2017
    Assignee: Universal Display Corporation
    Inventors: Ruiqing Ma, Chuanjun Xia, Prashant Mandlik
  • Patent number: 9735316
    Abstract: A method for manufacturing a high voltage LED flip chip is provided, including: providing a substrate; forming an epitaxy stacking layer on the substrate; etching the epitaxy stacking layer to form a first groove and a Mesa-platform on each chip-unit region; forming a first electrode on each of the Mesa-platforms, wherein the first electrodes on two neighboring chip-unit regions form a second groove; forming a first insulation layer covering the Mesa-platforms and the first electrodes, filling the second groove and partially filling the first grooves to form a third groove; etching the first insulation layer to form fourth groove; and forming an interconnection electrode, wherein the interconnection electrode fills the third groove and the fourth groove, two neighboring interconnection electrodes form a fifth groove, the interconnection electrode connects the first electrode on one chip-unit region and the first semiconductor layer on the other chip-unit region. LED formed has improved performance.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: August 15, 2017
    Assignee: Enraytek Optoelectronics Co., Ltd.
    Inventors: Huiwen Xu, Yu Zhang, Qiming Li
  • Patent number: 9735049
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of conductors thereon that are adjacent to each other, and a valley between the two sections of the conductors, filling the valley with a first passivation material to form a passivation valley, applying a second passivation material overlying the two sections of conductors and the passivation valley and over the substrate, and removing the second passivation material overlying the two sections of conductors and the passivation valley, and the second passivation material over the substrate but not in contact with the two sections of conductors and the passivation valley.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lee, Hung-Che Liao, Kun-Tsang Chuang, Wei-Chung Lu
  • Patent number: 9721915
    Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 1, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Motoru Yoshida, Kazuyo Endo, Jun Fujita, Hiroaki Okabe, Kazuyuki Sugahara
  • Patent number: 9721888
    Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Fei Liu, Adam M. Pyzyna
  • Patent number: 9721898
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
  • Patent number: 9721890
    Abstract: A system-on-chip includes a substrate, a plurality of unit cells on the substrate, a first power mesh, and a second power mesh. The first power mesh includes a power rail that is connected to power terminals of the plurality of unit cells and is provided in a first metallization layer. The first power mesh also includes a power strap in a second metallization layer. The second power mesh is provided in a third metallization layer and a fourth metallization layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hun Heo
  • Patent number: 9716071
    Abstract: A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 25, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Ji Yeon Ryu, Byong Jin Kim, Jae Beum Shim
  • Patent number: 9711529
    Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: July 18, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Huayong Hu, Lei Ye
  • Patent number: 9711468
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Patent number: 9711427
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 9698142
    Abstract: A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding. Thus, an applied stress to a lower structure in the pad region is also reduced. As a result, the buffer layer prevents formation of an electrical bridge between the pad region and the peripheral region.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 4, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jung Sam Kim
  • Patent number: 9699897
    Abstract: One or more techniques or systems for mitigating peeling associated with a pad, such as a pad of a semiconductor, are provided herein. In some embodiments, a pad structure for mitigating peeling comprises a bond region located above a first region. In some embodiments, a first inter-layer dielectric region associated with the first region is formed in an inter-layer region under the pad. Additionally, a first inter-metal dielectric region associated with the first region is formed in an inter-metal region under the inter-layer region. In some embodiments, the first inter-metal region is formed under the first inter-layer region. In this manner, peeling associated with the pad structure is mitigated, at least because the first inter-metal dielectric region comprises dielectric material and the first inter-layer dielectric region comprises dielectric material, thus forming a dielectric-dielectric interface between the first inter-metal dielectric region and the inter-layer dielectric region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Szu-Ying Chen, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chia-Wei Liu, Chung-Chuan Tseng
  • Patent number: 9698344
    Abstract: Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: July 4, 2017
    Assignee: INTEL CORPORATION
    Inventor: DerChang Kau
  • Patent number: 9691840
    Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 9685531
    Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 9685405
    Abstract: A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 20, 2017
    Assignee: NXP USA, INC.
    Inventors: Mehul D. Shroff, Douglas M. Reber, Edward O. Travis
  • Patent number: 9685555
    Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 20, 2017
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Nicolas Loubet, Chun-chen Yeh, Ruilong Xie, Xiuyu Cai