At Least One Layer Containing Chromium Or Nickel Patents (Class 257/766)
  • Patent number: 11257745
    Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Veronica Strong, Kristof Darmawikarta, Arnab Sarkar
  • Patent number: 11037732
    Abstract: A multilayered capacitor includes a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes; and external electrodes disposed on both end portions of the capacitor body and connected to exposed portions of the internal electrodes, respectively. Each of the external electrodes includes a conductive layer formed on the capacitor body and connected to the internal electrodes; an inner plated layer including nickel (Ni) and phosphorus (P), and covering the conductive layer; and an outer plated layer including palladium (Pd) and phosphorus (P), and covering the inner plated layer.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Geum Kim, Byeong Cheol Moon, Kun Hoi Koo, Jung Min Kim
  • Patent number: 10741403
    Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: August 11, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Katja Väyrynen, Mikko Ritala, Markku Leskelä
  • Patent number: 10720534
    Abstract: A pressure sensor includes a base including an accommodation portion, a pressure sensor element disposed in the accommodation portion, and a lead portion electrically-connected to the pressure sensor element, including a terminal portion provided along a lower surface of the base, and being exposed to an outside of the base, where the terminal portion includes a recessed groove portion provided on a second surface which is an opposite surface of a first surface facing the body, and where the recessed groove portion divides at the second surface, a first region including a tip of the terminal portion and a second region next to the first region and away from the tip of the terminal portion.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 21, 2020
    Assignee: FUJIKURA LTD.
    Inventor: Michikazu Tomita
  • Patent number: 10600736
    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 24, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Shinzo Ishibe
  • Patent number: 10544040
    Abstract: A method of attaching a MEMS die to a mounting surface includes coating an inside surface of a pressure port of a fluid inlet member with a layer of solder mask, the fluid inlet member having a first axial end, a second axial end, and a port opening of the pressure port formed in the second axial end of the fluid inlet member. A solder preform is disposed on the mounting surface of the fluid inlet member and a MEMS die is disposed on the solder preform. The solder preform is heated in a re-flow operation to attach the MEMS die to the mounting surface, wherein the solder mask within the pressure port prevents molten solder from entering the pressure port during the re-flow operation.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 28, 2020
    Assignee: DunAn Microstaq, Inc.
    Inventors: Wayne C. Long, Joe A. Ojeda, Joseph L. Nguyen
  • Patent number: 10468261
    Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 5, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Katja Väyrynen, Mikko Ritala, Markku Leskelä
  • Patent number: 10347711
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Deok-Sin Kil, Hee-Young Jeon
  • Patent number: 10192970
    Abstract: A simultaneous ohmic contact to silicon carbide includes a mixture of platinum, titanium, and silicon compounds deposited on a silicon carbide substrate. The silicon carbide substrate includes an n-type surface and a p-type surface.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: January 29, 2019
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Robert S. Okojie
  • Patent number: 9801288
    Abstract: A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Tong Hsing Electronic Industries, Ltd.
    Inventors: Chien-Cheng Wei, Ta-Hsiang Chiang
  • Patent number: 9373595
    Abstract: In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal (4) of an electronic component (1) and an electrode terminal (5) of a substrate (2) contains an alloy (8) and a metal (9) having a lower modulus of elasticity than the alloy (8). The junction has a cross section structure in which the alloy (8) is surrounded by the metal (9) having the lower modulus of elasticity.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 21, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daisuke Sakurai, Kazuya Usirokawa, Kiyomi Hagihara
  • Patent number: 9292041
    Abstract: A touch panel includes a substrate, a first adhesive layer stacked on the substrate, a first conductive layer stacked on the first adhesive layer and having a first electrode pattern, a second adhesive layer stacked on the first adhesive layer and the first conductive layer, and a second conductive layer stacked on the second adhesive layer and having a second electrode pattern. The first electrode pattern includes first island-like electrode portions and first connecting portions electrically interconnecting the first island-like electrode portions. The second electrode pattern includes a plurality of second island-like electrode portions formed in a spaced apart relationship in a second direction intersecting a first direction so as not to be overlapped with the first electrode pattern, and second connecting portions electrically interconnecting the second island-like electrode portions over via the first connecting portions.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 22, 2016
    Assignee: Nissha Printing Co., Ltd.
    Inventors: Katsumi Tokuno, Kazuhiko Takahata
  • Patent number: 9234274
    Abstract: Methods for deposition of elemental metal films on surfaces using metal coordination complexes are provided. The metal complexes comprise thiophene, pyrrole or salen-based ligands. A substrate surface may be contacted with a vapor phase metal coordination complex such that a layer is formed on the surface comprising the metal coordination complex bound to the surface by the metal. The bound metal complex may then be contacted with a reducing gas such that an exchange reaction occurs between the bound metal coordination complex and the reducing gas, thereby dissociating the bound metal complex and producing a first layer of elemental metal on the surface of the substrate. The process can be repeated for additional layers.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Bhaskar Jyoti Bhuyan, Anshita Gairola
  • Patent number: 9190296
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Publication number: 20150145136
    Abstract: In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Honeywell International Inc.
    Inventor: Ronald J. Jensen
  • Patent number: 9035459
    Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Harry D. Cox, Timothy H. Daubenspeck, Krystyna W. Semkow, Timothy D. Sullivan
  • Patent number: 9030017
    Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9018760
    Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan, Brian R. Sundlof
  • Publication number: 20150108650
    Abstract: The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure.
    Type: Application
    Filed: May 7, 2014
    Publication date: April 23, 2015
    Applicant: LEXTAR ELECTRONICS CORPORATION
    Inventor: Yi-Jyun CHEN
  • Patent number: 9006899
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Patent number: 8981578
    Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Inventors: Matthew E. Last, Lili Huang, Seung Jae Hong, Ralph E. Kauffman, Tongbi Tom Jiang
  • Publication number: 20150069613
    Abstract: According to one exemplary embodiment, a semiconductor device includes a chip main body; a first layer that is provided on the chip main body and contains nickel and phosphorus; and a second layer that is provided on the first layer and contains nickel and phosphorus and has a higher phosphorus concentration than that of the first layer.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya SHIRAISHI, Ryota YOSHIOKA
  • Publication number: 20150069614
    Abstract: A semiconductor device includes a first metal layer disposed on a first surface of a semiconductor layer, or a portion thereof. The first metal layer is made of a first metal. At least a portion of the first metal layer is crystallized. A second metal layer is disposed on a second surface of the semiconductor layer. The second surface is opposite the first surface. The second metal layer is also made of the first metal and has at least a portion that is crystallized. In some embodiments, the first metal may be nickel. In some embodiments, the semiconductor device may be a power semiconductor device, such as an insulated gate bipolar transistor and a fast recovery diode.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie NISHIKAWA, Hironobu SHIBATA, Nobuhiro TAKAHASHI
  • Patent number: 8970037
    Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 3, 2015
    Assignee: TDK Corporation
    Inventors: Kenichi Yoshida, Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Publication number: 20150054162
    Abstract: A chip package substrate includes a base substrate including via holes. A circuit pattern layer is formed in an area of the base substrate corresponding to the via holes, and a first plated layer formed on the other surface opposite to one surface of the circuit pattern layer in contact with the via holes.
    Type: Application
    Filed: April 12, 2013
    Publication date: February 26, 2015
    Inventor: Hong Il Kim
  • Patent number: 8963331
    Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tianhong Zhang, Akram Ditali
  • Publication number: 20150048510
    Abstract: A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive.
    Type: Application
    Filed: April 22, 2013
    Publication date: February 19, 2015
    Inventors: Manabu Tomisaka, Yoshifumi Okabe, Mikimasa Suzuki
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946903
    Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20150021771
    Abstract: Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventor: Jing-Cheng LIN
  • Publication number: 20150008583
    Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventor: Mark A. Gerber
  • Patent number: 8896122
    Abstract: Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: November 25, 2014
    Assignee: Cree, Inc.
    Inventors: Van Mieczkowski, Helmut Hagleitner, Kevin Haberern
  • Patent number: 8884310
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 11, 2014
    Assignees: SunEdison Semiconductor Limited (UEN201334164H), KSU Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry
  • Patent number: 8884432
    Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 11, 2014
    Assignee: Tessera, Inc.
    Inventors: Kazuo Sakuma, Philip Damberg, Belgacem Haba
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8822327
    Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 2, 2014
    Assignee: Infineon Technologies AG
    Inventors: Johann Gatterbauer, Bernhard Weidgans
  • Publication number: 20140203438
    Abstract: Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Jie Chen, Ying-Ju Chen
  • Patent number: 8760882
    Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 24, 2014
    Assignee: Xintec Inc.
    Inventors: Yi-Ming Chang, I-Min Lin, Po-Shen Lin
  • Publication number: 20140167268
    Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 8754528
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a crystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Maki Sugai, Eiji Muramoto, Shinya Nunoue
  • Patent number: 8749066
    Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tianhong Zhang, Akram Ditali
  • Patent number: 8742571
    Abstract: A diode arrangement includes a diode and two electrodes. Each electrode is connected to the diode in an electrically conductive manner via a soldered connection on one of two oppositely arranged contact surfaces of the diode. The contact surfaces of the diode are formed substantially by the surfaces of a lower side and an upper side of the diode and are contacted with the contact extensions of the electrodes via the soldered connection. The contact extensions forming counter contact surfaces are substantially congruent with the contact surfaces of the diode.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 3, 2014
    Assignee: Pac Tech—Packaging Technologies GmbH
    Inventors: Elke Zakel, Thorsten Teutsch, Ghassem Azdasht, Siavash Tabrizi
  • Publication number: 20140145340
    Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Inventor: Rajendra D. Pendse
  • Patent number: 8735273
    Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Yi-Wen Wu, Hsiu-Jen Lin, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Publication number: 20140138836
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Takaharu NAGASAWA
  • Publication number: 20140131875
    Abstract: In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 8720048
    Abstract: A method of manufacturing a printed circuit board includes arranging a core layer in which a bending prevention portion of at least two layers that are metal layers having different thermal expansion coefficients is disposed between a plurality of insulating members; forming a circuit pattern so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and forming an insulating layer including an opening portion that exposes the circuit pattern on the core layer.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi Sun Hwang, Jae Joon Lee, Myung Sam Kang
  • Publication number: 20140124792
    Abstract: Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: Cree, Inc.
    Inventors: Helmut Hagleitner, Fabian Radulescu, Daniel Namishia
  • Publication number: 20140110848
    Abstract: Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: U.S. ARMY RESEARCH LABORATORY ATTN: RDRL-LOC-I
    Inventors: Patrick J. Taylor, Sudhir Trivedi, Wendy L. Sarney
  • Publication number: 20140097542
    Abstract: Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.
    Type: Application
    Filed: August 26, 2013
    Publication date: April 10, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan