Refractory Or Platinum Group Metal Or Alloy Or Silicide Thereof Patents (Class 257/768)
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Patent number: 7799682Abstract: By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.Type: GrantFiled: April 9, 2007Date of Patent: September 21, 2010Assignee: GlobalFoundries Inc.Inventors: Sven Beyer, Patrick Press, Thomas Feudel
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Patent number: 7786837Abstract: A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.Type: GrantFiled: June 12, 2007Date of Patent: August 31, 2010Inventor: François Hébert
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Patent number: 7777344Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.Type: GrantFiled: April 11, 2007Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Publication number: 20100171221Abstract: The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin.Type: ApplicationFiled: July 7, 2009Publication date: July 8, 2010Inventor: Akihiro CHIDA
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Publication number: 20100171188Abstract: A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Inventors: Hsiang-Lan Lung, Erh-Kun Lai
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Patent number: 7750471Abstract: Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed.Type: GrantFiled: June 28, 2007Date of Patent: July 6, 2010Assignee: Intel CorporationInventor: Pushkar Ranade
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Publication number: 20100155955Abstract: A method of manufacturing a System In Package (SIP) and devices thereof. A method of manufacturing a SIP may include providing a first chip having a first substrate region and/or a first metal connection portion. A method of manufacturing a SIP may include providing a second chip having a second substrate region and/or a second metal connection portion. A method of manufacturing a SIP may include bonding a first metal connection portion with a second metal connection portion, which may stack a second chip with a first chip. A method of manufacturing a SIP may include subjecting a second substrate region to reactive ion etching to expose a portion of a second metal connection portion and/or to form a deep contact hole. A method of manufacturing a SIP may include treating a surface of a deep contact hole with tetra-methyl ammonium hydroxide and/or nitric acid.Type: ApplicationFiled: November 17, 2009Publication date: June 24, 2010Inventor: Chung-Kyung Jung
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Patent number: 7732331Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.Type: GrantFiled: November 16, 2004Date of Patent: June 8, 2010Assignee: ASM International N.V.Inventors: Ki-Bum Kim, Pekka J. Soininen, Ivo Raaijmakers
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Patent number: 7719044Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature a within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.Type: GrantFiled: August 13, 2003Date of Patent: May 18, 2010Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7692301Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.Type: GrantFiled: May 21, 2007Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
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Patent number: 7655567Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.Type: GrantFiled: July 24, 2007Date of Patent: February 2, 2010Assignee: Novellus Systems, Inc.Inventors: Juwen Gao, Lana Hiului Chan, Panya Wongsenakhum
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Patent number: 7649263Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.Type: GrantFiled: November 23, 2007Date of Patent: January 19, 2010Assignee: United Microelectronics Corp.Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
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Patent number: 7638800Abstract: First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and patterned to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads.Type: GrantFiled: July 29, 2002Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hee Yu, Mun-Pyo Hong, Soo-Guy Rho, Nam-Seok Rho, Keun-Kyu Song, Hee-Hwan Choe, Bo-Sung Kim, Sang-Gab Kim, Sung-Chul Kang, Hong-Sick Park
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Publication number: 20090315185Abstract: A method for forming dual salicide contacts includes depositing a low or mid-gap work function metal selectively on an NMOS source/drain (S/D) region of a semiconductor device via electroless deposition; depositing a high work function metal selectively over the low work function metal and a PMOS source/drain (S/D) region of a semiconductor device via electroless deposition; annealing the semiconductor device to form a silicide of the low work function metal over the NMOS source/drain (S/D) region and a silicide of the high work function metal over the PMOS source/drain (S/D) region; and performing a SALICIDE etch to remove the unreacted metals from all regions of the substrate.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Inventors: Boyan Boyanov, Ramanan Chebiam
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Patent number: 7629254Abstract: Embodiments relater to a semiconductor device and a method of fabricating the same. A source/drain area may be formed by using the spacer having the dual structure of the oxide layer and nitride layer. After etching a part of the oxide layer, the salicide layer may be formed on the gate electrode and the source/drain area, and the spacer may be removed. The contact area may be ensured, so a higher degree of integration may be achieved.Type: GrantFiled: September 4, 2007Date of Patent: December 8, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Jin-Ha Park
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Publication number: 20090294858Abstract: A transistor contact over a gate active area includes a transistor gate formed on a substrate of an integrated circuit. A gate insulator is formed beneath the transistor gate and helps define an active area for the transistor gate. An insulating layer is formed over the transistor gate. A metal contact plug is formed within a portion of the insulating layer that lies over the active area such that the metal contact plug forms an electrical contact with the transistor gate.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Applicant: Omnivision Technologies, Inc.Inventor: Howard E. Rhodes
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Publication number: 20090289370Abstract: Low contact resistance semiconductor devices and methods for fabricating such semiconductor devices are provided. In accordance with one exemplary embodiment, a method comprises depositing an insulating material overlying a metal silicide region and etching a contact opening within the insulating material and exposing the metal silicide region. The contact opening is at least partially bottom-filled with substantially pure cobalt. A conductor is deposited in the contact opening if, after the step of at least partially bottom-filling, the contact opening is not filled with the substantially pure cobalt.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Paul R. BESSER, Andreas H. KNORR
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Patent number: 7615868Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.Type: GrantFiled: January 8, 2008Date of Patent: November 10, 2009Assignee: NEC CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
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Patent number: 7586196Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.Type: GrantFiled: August 15, 2007Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Publication number: 20090174078Abstract: Provided is a semiconductor device and method of manufacturing the same. The semiconductor device may include a base material and a compound layer on the base material including a mixture of a non-adhesive organic material and a non-oxidizing metal material.Type: ApplicationFiled: January 5, 2009Publication date: July 9, 2009Inventors: Hyeck-Jin Jeong, Seon-Ju Oh, Yong-Ki Park, Heui-Seog Kim
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Publication number: 20090166875Abstract: Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: SAMEER PENDHARKAR, Binghua Hu
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Publication number: 20090146309Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.Type: ApplicationFiled: November 20, 2008Publication date: June 11, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
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Patent number: 7541284Abstract: A ruthenium film deposition method is disclosed. In one embodiment of the method, a first ruthenium film is deposited by using a PEALD process until a substrate is substantially entirely covered with the first ruthenium film. Then, a second ruthenium film is deposited on the first ruthenium film by using a thermal ALD process having a higher deposition speed than that of the PEALD process. In the method, a ruthenium metal film having a high density is formed in a short time by combining a PEALD process of depositing a ruthenium film at a low deposition speed and a deposition process of depositing a ruthenium film at a higher deposition speed. Accordingly, it is possible to form a ruthenium film having high density, a smooth surface, good adhesiveness, and a short incubation period.Type: GrantFiled: February 14, 2007Date of Patent: June 2, 2009Assignee: ASM Genitech Korea Ltd.Inventor: Hyung-Sang Park
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Publication number: 20090051037Abstract: A semiconductor device relating to the present invention has multiple gate electrodes arranged on a semiconductor substrate at a narrow spacing and an interlayer insulating film covering the gate electrodes. The interlayer insulating film consists of a hygroscopic insulating film filling gate electrode spacing with a thinner thickness on the gate electrodes than the film thickness on the flat surface of the semiconductor substrate and low-hygroscopic insulating film formed on the hygroscopic insulating film. This structure enables suppressing an increase of contact resistance due to H2O liberated from the hygroscopic insulating film even if very fine contact is formed between the adjacent gate electrodes.Type: ApplicationFiled: August 15, 2008Publication date: February 26, 2009Inventor: Masahiro JOEI
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Patent number: 7494607Abstract: The present invention is directed to an electroconductive thick film composition comprising: (a) electroconductive metal particles selected from (1) Al, Cu, Au, Ag, Pd and Pt; (2) alloy of Al, Cu, Au, Ag, Pd and Pt; and (3) mixtures thereof; (3) glass frit wherein said glass frit is Pb-free; dispersed in (d) an organic medium, and wherein the average diameter of said electroconductive metal particles is in the range of 0.5-10.0 ?m. The present invention is further directed to an electrode formed from the composition as detailed above and a semiconductor device(s) (for example, a solar cell) comprising said electrode.Type: GrantFiled: April 14, 2005Date of Patent: February 24, 2009Assignee: E.I. du Pont de Nemours and CompanyInventors: Yueli Wang, Kenneth Warren Hang
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Patent number: 7479687Abstract: Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly depositing a seed layer on the activated non-continuous metal layer and the plurality of non-deposited regions within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free metal filled recess.Type: GrantFiled: November 15, 2005Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Thomas S. Dory, Kenneth N. Wong
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Patent number: 7479682Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).Type: GrantFiled: February 28, 2007Date of Patent: January 20, 2009Assignee: Oki Electric Industry Co., Ltd.Inventors: Norio Hirashita, Takashi Ichimori
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Publication number: 20080309442Abstract: A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.Type: ApplicationFiled: June 12, 2007Publication date: December 18, 2008Inventor: Francois Hebert
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Patent number: 7449782Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: May 4, 2004Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
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Patent number: 7436067Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g., ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.Type: GrantFiled: June 7, 2005Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Gurtej Sandhu
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Patent number: 7432202Abstract: A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold. An apparatus includes a package substrate including a plurality of land contacts wherein each of the plurality of land contacts includes a coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold.Type: GrantFiled: December 28, 2005Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Bijay S. Saha, Munehiro Toyama, Ehab A. Nasir, Omar J. Bchir, Charavana K. Gurumurthy
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Publication number: 20080237871Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2).Type: ApplicationFiled: October 27, 2006Publication date: October 2, 2008Applicant: NXP B.V.Inventors: Vijayaraghavan Madakasira, Prabhat Agarwal, Johannes Josephus Theodorus Marinus Donkers, Mark Van Dal
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Patent number: 7429781Abstract: A memory chip package with a controller die on a first side of a printed circuit board and a memory die on a second side of the same printed circuit board. The memory chip package is integrated into a microprocessor controlled device or alternatively is integrated into a portable memory card.Type: GrantFiled: January 25, 2006Date of Patent: September 30, 2008Assignee: SanDisk CorporationInventor: Robert F. Wallace
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Patent number: 7422707Abstract: A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns, a first resin that has a softening point between 80-260° C., solvent, curing agent, and a second resin, wherein at room temperature the first resin is substantially soluble in the solvent.Type: GrantFiled: January 10, 2007Date of Patent: September 9, 2008Assignee: National Starch and Chemical Investment Holding CorporationInventor: Qizhuo Zhuo
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Patent number: 7420998Abstract: A semiconductor laser device has a front surface electrode formed by Au plating, a rear surface electrode formed by Au plating, an anti-adhesive film only on the front surface electrode and made of a material that does not react with Au, and a coating film that covers an end face on a light emitting side and an end face opposite the light emitting side. The anti-adhesive films are located on the four corners of the front surface electrode.Type: GrantFiled: March 23, 2005Date of Patent: September 2, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Junichi Horie
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Patent number: 7420227Abstract: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.Type: GrantFiled: June 22, 2005Date of Patent: September 2, 2008Assignee: National Chiao Tung UniversityInventors: Edward Yi Chang, Shang-Wen Chang, Cheng-Shih Lee
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Patent number: 7414291Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.Type: GrantFiled: April 6, 2005Date of Patent: August 19, 2008Assignee: Elpida Memory, Inc.Inventors: Shigetomi Michimata, Ryo Nagai, Satoru Yamada, Yoshitaka Nakamura, Ryoichi Nakamura
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Publication number: 20080179752Abstract: A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.Type: ApplicationFiled: September 11, 2007Publication date: July 31, 2008Inventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga
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Patent number: 7399702Abstract: Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over a semiconductive material. The device is heated, causing atoms of the semiconductive material to move towards and bond to the atoms of the second metal, leaving vacancies in the semiconductive material, and causing atoms of the first metal to move into the vacancies in the semiconductive material.Type: GrantFiled: February 1, 2005Date of Patent: July 15, 2008Assignee: Infineon Technologies AGInventors: Chan Lim, Bum Ki Moon
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Patent number: 7385287Abstract: A method of forming a feature in a low-k dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A CO conditioning is preformed on the at least one feature after the at least one feature is etched. The patterned photoresist mask is stripped after the CO conditioning.Type: GrantFiled: May 3, 2007Date of Patent: June 10, 2008Assignee: LAM Research CorporationInventors: Siyi Li, Helen H. Zhu, Howard Dang, Thomas S. Choi, Peter Loewenhardt
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Patent number: 7368823Abstract: A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer, and (c) causing the carbon nanotubes to grow by heating the catalyst layer by thermal CVD so that the carbon nanotubes serve as the interconnection part. The growth mode control layer is formed by sputtering or vacuum deposition in an atmospheric gas, using a metal selected from a group of Ti, Mo, V, Nb, and W. The growth mode is controlled in accordance with a predetermined concentration of oxygen gas of the atmospheric gas.Type: GrantFiled: July 3, 2006Date of Patent: May 6, 2008Assignee: Fujitsu LimitedInventors: Masahiro Horibe, Akio Kawabata, Mizuhisa Nihei
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Patent number: 7348265Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.Type: GrantFiled: March 1, 2004Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventor: Jiong-Ping Lu
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Patent number: 7332435Abstract: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.Type: GrantFiled: March 4, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shih-Wei Chou, Hung-Wen Su, Minghsing Tsai
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Patent number: 7323783Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.Type: GrantFiled: December 6, 2004Date of Patent: January 29, 2008Assignee: NEC CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
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Patent number: 7303988Abstract: Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by patterning the first metal layer, the etching stopper layer, and the second metal layer, wherein the first metal layer pattern is formed as a lower metal line; forming a connection contact in form of a plug by selectively etching the second metal layer pattern until the etching stopper layer is exposed; forming an interlayer insulating layer to cover the connection contact and the first metal layer pattern; and exposing an upper surface of the connection contact by planarizing the interlayer insulating layer.Type: GrantFiled: December 30, 2004Date of Patent: December 4, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Sang Chul Shim
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Patent number: 7291920Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.Type: GrantFiled: August 26, 2005Date of Patent: November 6, 2007Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7256498Abstract: Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.Type: GrantFiled: July 28, 2005Date of Patent: August 14, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chun Huang, Jyu-Horng Shieh, Ju-Wang Hsu
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Patent number: 7244996Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).Type: GrantFiled: April 5, 2001Date of Patent: July 17, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Norio Hirashita, Takashi Ichimori
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Patent number: 7230304Abstract: An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road side transformer using thereof. The contact member is composed of a base member made of high conductive metal, and a contact layer made of refractory metal and high conductive metal, and the contact layer is formed of a plurality of thermal sprayed layers.Type: GrantFiled: January 3, 2005Date of Patent: June 12, 2007Assignee: Hitachi, Ltd.Inventors: Shigeru Kikuchi, Masato Kobayashi, Kenji Tsuchiya, Noboru Baba, Takashi Sato
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Patent number: 7180109Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.Type: GrantFiled: August 18, 2004Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: Robert S. Chau, Doulgas Barlage, Been-Yih Jin