Of Specified Configuration Patents (Class 257/773)
  • Patent number: 9839128
    Abstract: An apparatus includes a printed circuit board. The printed circuit board includes at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The printed circuit board includes a second dielectric layer on top of the at least one conductive layer. The printed circuit board includes a thermal pad on top of the second dielectric layer. The printed circuit board is fabricated by forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The printed circuit board is fabricated by backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventor: Phillip D. Isaacs
  • Patent number: 9831214
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes through-vias, an integrated circuit die mounting region, and a material disposed around and between the through-vias and the integrated circuit die mounting region. An interconnect structure is disposed over the material, the through-vias, and the integrated circuit die mounting region. The interconnect structure includes a dummy feature disposed proximate one of the through-vias.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9831121
    Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Okawa, Shigeki Kobayashi, Kei Sakamoto, Ryosuke Sawabe
  • Patent number: 9831166
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 9831216
    Abstract: The present disclosure discloses a chip packaging module, including: a first chip, where a first pad is disposed on a side neighboring to a front surface of the first chip; at least a second chip, where at least one second chip is disposed on a rear side of the first chip, each second chip has a second pad, and wherein the first pad of the first chip is connected to the second pad of the second chip via a redistribution layer. According to the chip packaging module in the present disclosure, a second chip is disposed on a rear side of a first chip, and a first pad is connected to a second pad via a redistribution layer. By means of a redistribution technology on surfaces of multiple chips, a lead of a pad on a front surface of a fingerprint recognition chip is masterly winded to the back for interconnection, so that an induction area on the front surface of the chip can fully contact with a human body.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 28, 2017
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Baoquan Wu, Wei Long
  • Patent number: 9824901
    Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Adel A. Elsherbini, Joshua D. Heppner, Shawna M. Liff
  • Patent number: 9818666
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 9812356
    Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Wook Hwang, Jong Hyun Lee, Jae Seok Yang, In Wook Oh, Hyun Jae Lee
  • Patent number: 9814166
    Abstract: A method of manufacturing electronic package module is provided. The method provides selective molding by attaching tapes on the circuit substrate on which electric components are mounted thereon, forming molding compound to cover the circuit substrate, and removing tapes along with the molding compound thereon.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 7, 2017
    Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Jen-Chun Chen, Tsung-Jung Cheng, Chia-Cheng Liu
  • Patent number: 9806013
    Abstract: A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises: a substrate having an electrically conductive portion thereon; a dielectric layer formed over the substrate; the dielectric layer comprising an opening over at least part of the electrically conductive portion; and a conductive pillar formed on the at least part of the electrically conductive portion; wherein the conductive pillar comprises walls defined by at least the opening of the dielectric layer and an opening of a patterned layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: October 31, 2017
    Assignee: Institute of Technical Education
    Inventors: Teck Kheng Lee, Bok Leng Ser
  • Patent number: 9793159
    Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus, Elliot N. Tan, Swaminathan Sivakumar
  • Patent number: 9786586
    Abstract: A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.
    Type: Grant
    Filed: August 21, 2016
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 9785740
    Abstract: A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data file that includes the layout pattern of the layout. The layout includes the one or more standard cells and placement and routing information generated by the one or more initial place and route operations. The method further comprises identifying one or more metal portions associated with one or more rails of the one or more standard cells of the layout. A metal fill operation is then performed using the input data file in order to generate a modified input data file. The metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 10, 2017
    Assignee: ARM Limited
    Inventor: Ivan Michael Lowe
  • Patent number: 9780031
    Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
  • Patent number: 9780095
    Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 3, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Houb Chun, Jeong-Sub Lim
  • Patent number: 9768221
    Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yen Wu, I-Chih Chen, Yi-Sheng Liu, Volume Chien, Fu-Tsun Tsai, Chi-Cherng Jeng, Ying-Hao Chen
  • Patent number: 9768031
    Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Cheng-Hsiung Tsai
  • Patent number: 9768028
    Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Theodore J. Letavic, Yun Shi, Santosh Sharma
  • Patent number: 9762140
    Abstract: A semiconductor device includes a semiconductor chip, a metal member, and a terminal. The semiconductor chip has an electrode. The metal member is electrically connected to the electrode. The terminal extends from the metal member to be connected to an external connection member. The terminal has a width-increased portion in a predetermined area beginning from a first end of the terminal that connects to the metal member.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 12, 2017
    Assignee: DENSO CORPORATION
    Inventor: Daisuke Fukuoka
  • Patent number: 9754946
    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee
  • Patent number: 9754789
    Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee, Byung-Sung Kim
  • Patent number: 9754819
    Abstract: A method of forming a semiconductor device includes: forming a lower trace in a lower dielectric layer; reducing a height of the lower trace a distance equal to gap height (g) to form an initial void region; filling the initial void region with an amorphous carbon layer; forming an upper dielectric layer above the amorphous carbon layer; covering the amorphous carbon layer with at least an oxide layer and a nitride layer; forming a hole in the oxide and nitride layers to expose a portion of the amorphous carbon layer; exposing the amorphous carbon layer to oxygen plasma to remove the amorphous carbon layer; sputtering a metal layer over the oxide layer and into a void created removal of the amorphous carbon layer to divide the void such that it includes an airgap; and forming an upper trace over the airgap.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9754851
    Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
  • Patent number: 9754704
    Abstract: A method of making a thin-film multi-layer micro-wire structure includes providing a substrate and a layer on the substrate with one or more micro-channels having a width less than or equal to 20 microns. A conductive material including silver nano-particles and having a percent ratio of silver that is greater than or equal to 40% by weight is located in the micro-channels and cured to form an electrically conductive micro-wire. The electrically conductive micro-wire has a width less than or equal to 20 microns and a depth less than or equal to 20 microns. Each micro-wire is electrolessly plated to form a plated layer located at least partially within each micro-channel between the micro-wire and the layer surface in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 5, 2017
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Roger G. Markham, Ronald Steven Cok, Yongcai Wang, Mitchell Lawrence Wright
  • Patent number: 9748200
    Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 29, 2017
    Assignee: Powertech Technology Inc.
    Inventor: Chia-Hang Chang
  • Patent number: 9740035
    Abstract: There is provided a flexible display having a new wire structure and a new insulating layer structure. A flexible display includes a flexible substrate having a first area and a second area. The second area is curved in a non-zero angle relative to the plane of the first area. The flexible display further includes a plurality of wires that extend over from the first area to the second area of the flexible substrate. Each of the wires is covered by an upper insulating pattern, which is separated from other upper insulating pattern. Each upper insulating pattern covering the wire has substantially the same trace pattern shape of the corresponding wire thereunder. Accordingly, by adopting the above-described wire structure and upper insulating layer structure, crack generation and propagation in the wires and the insulating layers from bending of the flexible display can be minimized.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 22, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Seyeoul Kwon, Sang Hyeon Kwak, Sangcheon Youn
  • Patent number: 9715965
    Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 25, 2017
    Assignee: ARM Limited
    Inventors: Lucian Shifren, Vikas Chandra, Mudit Bhargava
  • Patent number: 9715290
    Abstract: A slim type touch panel is provided. The slim type touch panel includes an upper substrate, a first sensor electrode layer disposed at a lower part of the upper substrate, an insulating film disposed at a lower part of the first sensor electrode layer, and a second sensor electrode layer disposed at a lower part of the insulating film, or includes a first sensor electrode cover sheet in which a sensor electrode layer is patterned, a first adhesive layer disposed at a lower part of the first sensor electrode cover sheet, and a film layer disposed at a lower part of the first adhesive layer and comprising a second sensor electrode layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Sub Kim, Hak Yeol Kim, Hoon Do Heo, Jin Goo Kang
  • Patent number: 9711476
    Abstract: A wiring board includes: an insulating layer; a pad including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the side surface and the lower surface of the pad are embedded in the insulating layer; and a metal post formed on the upper surface of the pad and including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein a narrowed portion is formed in the side surface of the metal post.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 18, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tomoyuki Shimodaira, Takahiro Rokugawa, Hitoshi Kondo
  • Patent number: 9711471
    Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: July 18, 2017
    Assignee: NXP USA, Inc.
    Inventors: Charaf-Eddine Souria, Gilles Montoriol, St├ęphane Damien Thuries
  • Patent number: 9698094
    Abstract: A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 4, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hiroharu Yanagisawa, Kazuhiro Kobayashi
  • Patent number: 9698097
    Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: July 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom
  • Patent number: 9691745
    Abstract: Embodiments of mechanisms of a semiconductor device package and package on package (PoP) structure are provided. The semiconductor device package includes a substrate and a metal pad formed on the substrate. The semiconductor device package further includes a conductive element formed on the metal pad, and the metal pad electrically contacts the conductive element, and at least a portion of the conductive element is embedded in a molding compound, and the conductive element has a recess configured to provide an additional bonding interfacial area.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: James Hu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9681543
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 13, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Travis L. Kerby, Casey Philip Rodriguez, Michael Raymond Weatherspoon
  • Patent number: 9679924
    Abstract: An array substrate and manufacturing method thereof, a display device are provided. The array substrate includes a display region and a non-display region; the non-display region includes a first laminated structure and a second laminated structure that are separately disposed on a base substrate, a gap between the first laminated structure and the second laminated structure constitutes a connecting hole; the first laminated structure includes a first via hole provided for exposing a first metal layer, the second laminated structure includes a second via hole provided for exposing a second metal layer, the first via hole and the second via hole are connected to a connecting hole via breaches on corresponding walls, and the first metal layer and the second metal are electrically connected with a conductive film.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 13, 2017
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Qiangqiang Luo, Xiaoyu Yang, Kiyoung Kwon, Zhenfang Li, Xiaojun Su
  • Patent number: 9674949
    Abstract: A stretchable wire assembly includes a metal wire coupled between two elastic substrates. The two elastic substrates are selectively coupled together, and the metal wire is attached to one or both elastic substrates at select locations. The form of the metal wire is such that when the elastic substrates are in a relaxed, or non-stretched, state the metal wire forms a tortuous path, such as a waveform, along the coupled elastic substrates. The tortuous path of the metal wire provides slack such that as the elastic substrates are stretched the slack is taken up. Once released, the elastic substrates move from the stretched position to the relaxed, non-stretched position, and slack is reintroduced into the metal wire in the form of the original tortuous path.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Flextronics AP, LLC
    Inventors: Weifeng Liu, Zhen Feng, Anwar Mohammed
  • Patent number: 9659858
    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/┬░ C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9659900
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Maxim Intergrated Products, Inc.
    Inventors: Xuejun Ying, Arkadii V. Samoilov, Peter McNally, Tyler Parent
  • Patent number: 9646982
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 9, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Weiting Wang, Fumiharu Nakajima, Yoko Yokoyama, Sadatoshi Murakami
  • Patent number: 9647054
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tsung-Yuan Yu
  • Patent number: 9640496
    Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 2, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Cheng-Hsien Hsieh
  • Patent number: 9633968
    Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 25, 2017
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Wael Zohni, Philip R. Osborn
  • Patent number: 9627318
    Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ling Mei Lin, Chun Li Wu, Yu-Pin Chang
  • Patent number: 9627307
    Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: April 18, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Cheng-Hao Ciou, Cheng-Chieh Wu, Kuang-Hsin Chen, Hsien-Wen Chen
  • Patent number: 9627365
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 9620510
    Abstract: A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed on a first side of the second conductive layer. The third conductive layer is disposed on a second side of the second conductive layer. The third conductive layer is disposed on a side of the second conductive layer. The second conductive layer has a thickness which is thicker than those of the first conductive layer and the third conductive layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9613934
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 9613966
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim
  • Patent number: 9607919
    Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Dong Hoon Lee, Do Hyung Kim, Seung Chul Han
  • Patent number: 9607958
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen