Of Specified Configuration Patents (Class 257/773)
  • Patent number: 9299647
    Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 29, 2016
    Assignee: General Electric Company
    Inventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Donald Paul Cunningham
  • Patent number: 9293438
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 22, 2016
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Casey Philip Rodriguez, Travis L. Kerby, Michael Raymond Weatherspoon
  • Patent number: 9287325
    Abstract: A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 9277639
    Abstract: The present invention provides a semiconductor circuit board in which a conductor portion is provided on an insulating substrate, wherein a surface roughness of a semiconductor element-mounting section of the conductor portion is 0.3 ?m or lower in arithmetic average roughness Ra, 2.5 ?m or lower in ten-point average roughness Rzjis, 2.0 ?m or smaller in maximum height Rz, and 0.5 ?m or lower in arithmetic average waviness Wa. Further, assuming that a thickness of the insulating substrate is t1 and a thickness of the conductor portion is t2, the thickness of t1 and t2 satisfy a relation: 0.1?t2/t1?50. Due to above structure, even if an amount of heat generation of the semiconductor element is increased, there can be provided a semiconductor circuit board and a semiconductor device having excellent TCT characteristics.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 1, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Masanori Hoshino
  • Patent number: 9270251
    Abstract: A carrier for mounting a piezoelectric device, e.g., a surface acoustic wave (SAW) device, on a circuit board and a method of mounting a piezoelectric device on a circuit board using such a carrier are disclosed. The carrier includes a carrier bottom, a plurality of metal contacts, and a carrier lid attached to the carrier bottom. The carrier bottom has an opening extending partially through the carrier bottom from a top surface thereof and the opening is configured such that when a piezoelectric device to be mounted in the carrier is inserted into the carrier bottom, the piezoelectric device is at least partially recessed within the carrier bottom. The metal contacts include a cantilevered end configured for electrical connection to a piezoelectric device. The carrier lid is configured to retain a piezoelectric device within the carrier bottom and to apply substantially even pressure across a top surface of a piezoelectric device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 23, 2016
    Assignee: Adaptive Methods, Inc.
    Inventors: Peter Owen, Conrad Zeglin, Barclay Roman, Mark Meister
  • Patent number: 9263421
    Abstract: A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Boon Seong Lee, Chee Voon Tan
  • Patent number: 9263405
    Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Yen-Ping Wang
  • Patent number: 9263297
    Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Tokyo Electron Limited
    Inventor: Anton deVilliers
  • Patent number: 9255001
    Abstract: A monopolar and bipolar micro device transfer head array and method of forming a monopolar and bipolar micro device transfer array are described. In an embodiment, a micro device transfer head array includes a base substrate, a first insulating layer formed over the base substrate, and an array of mesa structures. A second insulating layer may be formed over the mesa structure, a patterned metal layer over the second insulating layer, and a dielectric layer covering the metal layer.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: February 9, 2016
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 9252135
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9251948
    Abstract: A transformer structure includes a first coil having two sections of spiral, with a top section including a plurality of metal layers occupying top X metal layers and a bottom section including a plurality of metal layers occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance of the first coil. A second coil of the transformer is disposed between the two sections of the first coil and includes a plurality of metal layers where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertical metal layers for the transformer structure.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Barry, Venkata Nr. Vanukuru
  • Patent number: 9245829
    Abstract: This invention provides a substrate structure that can effectively prevent scattering of solder balls which are produced due to explosion attributable to evaporation of flux during reflow soldering, and spreading of molten solder to the surroundings. On a substrate, a semiconductor chip is mounted via solder paste. The substrate is provided with a groove portion which continuously or discontinuously surrounds the solder paste.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 26, 2016
    Assignee: OMRON Corporation
    Inventors: Shintaro Hara, Shoichi Konagata, Yuzo Iwasaki, Tomonori Shiraishi
  • Patent number: 9245770
    Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: January 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, KooHong Lee, JaeHak Yee, YoungChul Kim, Lan Hoang, Pandi C. Marimuthu, Steve Anderson, HeeJo Chi
  • Patent number: 9245824
    Abstract: Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is deposited in the hole such that the stress-abating dielectric material is disposed at least laterally from the first dielectric material. Further, a second etching through at least a semiconductor material of a semiconductor layer that is disposed below the wiring layer is performed, where the second etching forms a via hole in the semiconductor material. Additionally, at least a portion of the via hole is filled with conductive material to form the through-via such that the stress-abating dielectric material, at least in the wiring layer, provides a buffer between the conductive material and the first dielectric material.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher V. Jahnes, Xiao Hu Liu, Bucknell C. Webb
  • Patent number: 9240374
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wei Shao, Wanbing Yi, Shunqiang Gong, Chao Zhu, Juan Boon Tan
  • Patent number: 9236439
    Abstract: A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: January 12, 2016
    Assignee: SK HYNIX INC.
    Inventor: Young Doo Jeong
  • Patent number: 9236333
    Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: January 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masato Numazaki
  • Patent number: 9236337
    Abstract: A semiconductor package includes a substrate having a vent hole extending through the substrate, a semiconductor chip mounted on an upper surface of the substrate, a plurality of solder ball pads formed on a lower surface of the substrate, and an encapsulant covering the upper surface of the substrate, the semiconductor chip, and an entirety of the lower surface of the substrate except for regions in which the solder ball pads are formed.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: January 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chan Park
  • Patent number: 9236325
    Abstract: Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher V. Jahnes, Xiao Hu Liu, Bucknell C. Webb
  • Patent number: 9236396
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 12, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Sateesh Koka, Senaka Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Rahul Sharangpani, George Matamis, Wei Zhao
  • Patent number: 9223305
    Abstract: A semiconductor manufacturing system includes circuitry configured to execute: displaying a screen for selecting an inspection set including inspection items having a manipulation item and/or a check item; retrieving the inspection items, arranging the inspection items in the order of workflow, and displaying each inspection item on a screen with an execution attribute indicating whether each inspection item is “automatic” or “manual” execution; receiving an inspection start command and reading the first inspection item from a storage unit. The circuitry also executes steps corresponding to the following cases (a) to (d) until there are no more inspection items: (a) the read-out inspection item being the manipulation item and “automatic”; (b) the read-out inspection item being the manipulation item and “manual”; (c) the read-out inspection item being the check item and “automatic”; and (d) the read-out inspection item being the check item and “manual”.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 29, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Gaku Ikeda, Koichi Miyashita, Takamasa Chikuma, Satoshi Gomi, Chunmui Li, Kunio Takano
  • Patent number: 9224649
    Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 29, 2015
    Assignee: TESSERA, INC.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 9224662
    Abstract: A semiconductor apparatus is disclosed, which includes a semiconductor element provided on a plane; a sealing resin that seals the semiconductor element; a terminal that is electrically connected to the semiconductor element and includes a part that projects from a predetermined surface of the sealing resin; and a concave portion that is recessed toward a side of the semiconductor element from the predetermined surface, when viewed in a direction perpendicular to the plane. A side of the concave portion on the side of the semiconductor element includes a rounded shape, when viewed in the direction perpendicular to the plane.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 29, 2015
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takuya Kadoguchi, Takahiro Hirano, Tomomi Okumura, Keita Fukutani, Masayoshi Nishihata
  • Patent number: 9215799
    Abstract: The terminal unit includes a main board, electronic components implemented on the main board, a sub-board covering above the electronic components and a frame member so disposed between the main board and the sub-board as to surround the electronic components. A flexible printed circuit covers an outer side of a wall portion of the frame member and is so wound around the frame member from upper and lower sides of the wall portion as to cover at least part of an inner side of the wall portion. A wiring pattern formed on the flexible printed circuit is electrically connected to the electronic components, and information to be protected that is stored on the electronic components becomes unreadable if the wiring pattern is cut off or short-circuited.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: December 15, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunjiro Takemori, Shigeru Narakino
  • Patent number: 9209165
    Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 8, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Michael H. S. Dayringer, R. David Hopkins, Alex Chow
  • Patent number: 9205669
    Abstract: Each data line includes base parts covering contact holes and line parts extending in an array direction of pixel circuits and connecting adjacent base parts to each other. The line parts have a smaller width in a direction perpendicular to the array direction than the base parts and are connected to the base parts while being offset in the direction perpendicular to the array direction from each other on both sides of at least two base parts that include first and second base parts. A connection position of the first base part with the line part on one side among both sides of the base units is located on the pixel circuit side with respect to the other side, and a connection position of the second base part on the one side is located on an opposite side to the pixel circuit side with respect to the other side.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 8, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kouji Ikeda, Masami Iseki
  • Patent number: 9209149
    Abstract: A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 ?m2 and about 1,300 ?m2.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fan Huang, Yi-Teh Chou, Ming-Da Cheng, Tin-Hao Kuo, Chung-Shi Liu, Chen-Shien Chen
  • Patent number: 9209123
    Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: December 8, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Teruhiro Kuwajima
  • Patent number: 9209131
    Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ryan David Lane, Urmi Ray
  • Patent number: 9202948
    Abstract: A solar cell includes a substrate, a selective emitter region which is positioned at the substrate and includes a lightly doped region and a heavily doped region, a first dielectric layer which is positioned on the selective emitter region and includes a plurality of first openings, which are separated from one another, and a plurality of second openings positioned around the plurality of first openings, a first electrode connected to the selective emitter region through the plurality of first openings and the plurality of second openings, and a second electrode which is positioned on the substrate and is connected to the substrate. The plurality of first openings and the plurality of second openings each have a different plane shape. The plane shape of the first opening has a line shape, and the plane shape of the second opening has a dot shape.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 1, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Younghyun Lee, Sangwook Park, Yoonsil Jin
  • Patent number: 9196508
    Abstract: A three-dimensional integrateds circuit structure includes a first metal circuit substrate, an interposer substrate disposed on the first metal circuit substrate and electrically connected therewith, and at least one semiconductor component disposed on the interposer substrate. The interposer substrate is used to dissipate the heat generated by the operation of the semiconductor components, so as to achieve the objective of increasing the lifespan of the semiconductor components.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: November 24, 2015
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kuo Kuo, Chia-Yi Hsiang, Hung-Tai Ku
  • Patent number: 9196580
    Abstract: A semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the passivation film and electrically connected to the electrode pad. The electrode pad is formed so as to be smaller in size than the bump electrode, and parts of the wiring on the uppermost layer are formed under the bump electrode. In this manner, it is possible to utilize the area under the bump electrode effectively without sacrificing flatness of the passivation film. As a result, the semiconductor device and the semiconductor package can be made smaller.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 24, 2015
    Assignee: LAPIS SEMINCONDUCTOR CO., LTD.
    Inventors: Hiroshi Yamamoto, Eiji Takeichi
  • Patent number: 9184143
    Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: November 10, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Yen-Ping Wang
  • Patent number: 9171743
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 9159697
    Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: October 13, 2015
    Assignee: WISTRON CORPORATION
    Inventors: Hui-Ying Chou, Lee-Chieh Kang
  • Patent number: 9159680
    Abstract: A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wook Park, Kwang-Yong Lee, Ho-Geon Song
  • Patent number: 9153531
    Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may be associated with a given tile type, and each tile type may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a given tile, which is sometimes also referred to as wire twisting. Wire twists may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires. At the same time, the twist region height (i.e., the region in the tile in which wires are twisted) may be reduced compared to conventional interconnect circuitry.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 6, 2015
    Assignee: Altera Corporation
    Inventors: Aron Joseph Roth, Michael Chan, Jeffrey Christopher Chromczak
  • Patent number: 9147681
    Abstract: An electronic system has first and second substantially vertical semiconductor structures. A first string of series-coupled first memory cells is adjacent to the first semiconductor structure, and a second string of series-coupled second memory cells is adjacent to the second semiconductor structure.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: September 29, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao Liu
  • Patent number: 9147611
    Abstract: Techniques and design methodologies for using a single mask set to create devices of different sizes are disclosed. A mask with a plurality of tiles is disclosed. Each of the tiles has a number of fixed resource blocks, multiple logic blocks and is surrounded by a scribe region. The tiles may be connected to one or more adjacent tiles through interconnect lines that enable the fixed resource blocks and logic blocks in one tile to communicate with the fixed resource and logic blocks in an adjacent tile. The mask set may be used to produce devices of different sizes. Using a mask set that can handle a variety of design sizes with varying resources may in turn reduce mask cost.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 29, 2015
    Assignee: Altera Corporation
    Inventors: Lawrence David Landis, Richard Price
  • Patent number: 9142469
    Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: September 22, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Tetsuji Takahashi
  • Patent number: 9142514
    Abstract: In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Lionel Chien Hui Tay, Frederick R. Dahilig
  • Patent number: 9136242
    Abstract: An electronic component including one or more legs for attachment to a circuit board, wherein at least one of said legs includes a spring-acting kink, arranged so as to offers resilience to relative displacement between the end of said leg and the body of said component. The kink may be substantially S-shaped, Z-shaped, U-shaped, wave-shaped or coil-shaped.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 15, 2015
    Assignee: Control Techniques Limited
    Inventor: Charles Anthony Cachia
  • Patent number: 9130024
    Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, David Ding-Chung Lu
  • Patent number: 9129906
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9131604
    Abstract: A communications path may be formed from intertwined conductive paths. The intertwined conductive paths may be formed from one or more layers of conductive material in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers, via layers, and a pad layer. The conductive paths may be formed from patterned conductive structures in the metal and pad layers. Vias in the via layers may be used to connect metal structures from multiple dielectric stack layers. The communications path may have segments in which the conductive paths run parallel to each other and may have cross-over regions in which the conductive paths cross one another without electrically connecting so that the paths twist about each other along their lengths. The communications path may be used to form a differential transmission line pair that distributes signals such as two-phase clock signals.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: September 8, 2015
    Assignee: Altera Corporation
    Inventors: Jeffrey T. Watt, Shuxian Chen
  • Patent number: 9129975
    Abstract: In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 8, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Kyoung Yeon Lee, Byong Jin Kim, Gi Jeong Kim
  • Patent number: 9117829
    Abstract: A semiconductor device includes a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface, an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate, a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate, and a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 25, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Akira Ide, Koji Torii
  • Patent number: 9117697
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 25, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Wen-Chi Cheng, Guo-Cheng Liao, Yi-Chuan Ding
  • Patent number: 9099364
    Abstract: Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 4, 2015
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventor: Shou-Chian Hsu
  • Patent number: 9093430
    Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin