Of Specified Configuration Patents (Class 257/773)
  • Patent number: 9117697
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 25, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Wen-Chi Cheng, Guo-Cheng Liao, Yi-Chuan Ding
  • Patent number: 9099364
    Abstract: Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 4, 2015
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventor: Shou-Chian Hsu
  • Patent number: 9093430
    Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
  • Patent number: 9093407
    Abstract: An organic light emitting diode (“OLED”) display includes: a substrate including a plurality of pixel areas; a plurality of switching transistors and a plurality of driving transistors on the substrate; and an organic light emitting element respectively connected to a switching transistor and a driving transistor among the plurality of switching transistors and the plurality of driving transistors. The driving transistor includes a semiconductor which overlaps a plurality of adjacent pixel areas.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun-Chol Bang, Won-Kyu Kwak, Se-Ho Kim
  • Patent number: 9076502
    Abstract: According to one embodiment, a non-volatile memory device includes a memory cell array and a coil provided closely to the memory cell array. The memory cell array includes memory cells provided above an underlying layer, and a first interconnection. The memory cells are aligned in a first direction perpendicular to the underlying layer. The first interconnection extends in a second direction perpendicular to the first direction. The coil includes a winding including a second interconnection extending in the second direction and sharing a central axis with the first interconnection, a first plug extending in the first direction and connected to the second interconnection, a third interconnection electrically connected to another end of the first plug and extending in a direction parallel to the underlying layer, and a second plug having one end electrically connected to the third interconnection, and extending in a direction opposite to the first direction.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroomi Nakajima
  • Patent number: 9070638
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 30, 2015
    Assignee: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 9064869
    Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 23, 2015
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Edward Fuergut, Gottfried Beer, Olaf Hohlfeld
  • Patent number: 9064867
    Abstract: Disclosed is a semiconductor device provided with: lower-layer wiring formed on a substrate, an interlayer insulating film covering the lower-layer wiring, and a first upper-layer wiring line (18b) and a second upper-layer wiring line (18c) arranged on the interlayer insulating film and intersecting with the lower-layer wiring, and a level-difference adjustment protrusion is provided between the first upper-layer wiring line (18b) and the second upper-layer wiring line (18c) adjacent to a side section of the lower-layer wiring.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: June 23, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Norihisa Asano, Kazuyoshi Imae
  • Patent number: 9059261
    Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: June 16, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
  • Patent number: 9059257
    Abstract: A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric cap in the cap opening and on the metal line; forming an interconnect dielectric layer over the dielectric cap and the second dielectric layer; forming an interconnect opening in the interconnect dielectric layer; removing a portion of the dielectric cap exposed by the interconnect opening selective to the interconnect dielectric layer, the second dielectric layer, and the metal line; and forming an interconnect structure in the interconnect opening, the interconnect structure comprising a contact line above a via, the via having an upper via portion with angled sidewalls and a lower via portion with substantially vertical sidewalls.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9059111
    Abstract: A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Edwards, Jeffrey P. Gambino, Charles F. Musante, Ping-Chuan Wang
  • Patent number: 9048241
    Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 2, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Won Chul Do, Pil Je Sung, Jin Hee Park, Do Hyung Kim, In Bae Park, Chang Min Lee, Yong Song, SungGeun Kang
  • Patent number: 9048235
    Abstract: A stack package includes a first semiconductor chip having a plurality of first pads, and a second semiconductor chip stacked on the first semiconductor chip and having a plurality of second pads corresponding to the first pads respectively, the second pads connected to the corresponding first pads. The first and second pads are arranged such that the first and second pads overlap with each other even after the first and second semiconductor chips are rotated relative to each other by a predetermined angle.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: June 2, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yun-Seok Choi
  • Publication number: 20150146122
    Abstract: A trace structure is proposed. The trace structure includes a substrate, a shorting bar on the substrate and a plurality of data lines or scan lines, whose one end is connected to the shorting bar, on the substrate. The trace structure also includes an excessive shorting bar on the substrate. A break on a data line or a scan line is repaired by connecting the broken data line or scan line with one of the excessive shorting bar or the rest of the shorting bars. The present invention also proposes a repair method and a LCD panel using the trace structure. The simple trace structure and easy break repair operation not only raises repair efficiency but also lessens repair time and saves cost.
    Type: Application
    Filed: December 13, 2013
    Publication date: May 28, 2015
    Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventor: Xiangyang Xu
  • Publication number: 20150145137
    Abstract: An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: STMicroelectronics Pte. Ltd
    Inventors: Calvin Leung, Olivier Le Neel
  • Publication number: 20150145128
    Abstract: A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Publication number: 20150145132
    Abstract: An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Arun RAMAKRISHNAN, Hongyu LI
  • Publication number: 20150145122
    Abstract: An embodiment includes an integrated circuit, comprising: a substrate; a first circuit formed on the substrate and coupled to a plurality of first pads on the substrate; and a second circuit formed on the substrate and coupled to a plurality of second pads on the substrate. The first pads are formed on a perimeter of the substrate; and the second pads extend from the perimeter of the substrate towards an interior of the substrate.
    Type: Application
    Filed: May 1, 2014
    Publication date: May 28, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young KOOG, Jiankang WANG, Harpreet GILL, Sunghwan MIN
  • Publication number: 20150145138
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Application
    Filed: February 5, 2015
    Publication date: May 28, 2015
    Applicant: INTEL CORPORATION
    Inventors: Robert L. Sankman, John S. Guzek
  • Publication number: 20150145107
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventor: Chee Yang Ng
  • Publication number: 20150145111
    Abstract: An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Manfred MENGEL, Edward Fuergut, Ralf Otremba, Juergen Hoegerl
  • Patent number: 9041206
    Abstract: A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Cheng-Jong Wang, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, U-Ting Chen, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 9041114
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Ide
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Patent number: 9041223
    Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuh Chern Shieh, Han-Ping Pu, Yu-Feng Chen, Tin-Hao Kuo
  • Patent number: 9041216
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Jen Sung, Yi-Nien Su
  • Patent number: 9041033
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a p-side electrode, a plurality of n-side electrodes, a first insulating film, a p-side interconnect unit, and an n-side interconnect unit. The p-side interconnect unit is provided on the first insulating film to connect to the p-side electrode through a first via piercing the first insulating film. The n-side interconnect unit is provided on the first insulating film to commonly connect to the plurality of n-side electrodes through a second via piercing the first insulating film. The plurality of n-side regions is separated from each other without being linked at the second surface. The p-side region is provided around each of the n-side regions at the second surface.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Akimoto, Yoshiaki Sugizaki, Akihiro Kojima, Miyoko Shimada, Hideyuki Tomizawa, Hideto Furuyama
  • Patent number: 9041207
    Abstract: An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Digvijay A. Raorane, Sairam Agraharam
  • Publication number: 20150137249
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: YI-TANG LIN, CLEMENT HSINGJEN WANN, NENG-KUO CHEN
  • Publication number: 20150137378
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20150137259
    Abstract: A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains. The pluralities of first and second crystal grains are separated from each other at a boundary formed between the first and second regions.
    Type: Application
    Filed: August 7, 2014
    Publication date: May 21, 2015
    Inventors: Hauk HAN, Yu Min KIM, Ki Hyun YOON, Myoung Bum LEE, Chang Won LEE, Joo Yeon HA
  • Publication number: 20150137381
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Inventors: WENG F. YAP, SCOTT M. HAYES, ALAN J. MAGNUS
  • Publication number: 20150137379
    Abstract: An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Publication number: 20150137322
    Abstract: A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.
    Type: Application
    Filed: December 10, 2014
    Publication date: May 21, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Publication number: 20150137380
    Abstract: An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: NXP B.V.
    Inventors: Michael Antoine Armand in 't Zandt, Viet Hoang Nguyen
  • Patent number: 9035462
    Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Qinghuang Lin
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Publication number: 20150130068
    Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu LIN, Kao-Cheng LIN, Li-Wen WANG, Yen-Huei CHEN
  • Publication number: 20150130066
    Abstract: An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Publication number: 20150130031
    Abstract: Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a plurality of first grooves arranged with a second distance that is smaller than the first distance, and a second groove enclosing the plurality of the segment regions with a third distance that is larger than the second distance.
    Type: Application
    Filed: October 24, 2014
    Publication date: May 14, 2015
    Inventor: Hiroshi YOSHINO
  • Publication number: 20150129986
    Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
    Type: Application
    Filed: December 23, 2014
    Publication date: May 14, 2015
    Inventors: Byron Neville Burgess, John K. Zahurak
  • Publication number: 20150130074
    Abstract: A semiconductor device may include: a wiring layer formed over an interlayer dielectric layer; and one or more wiring characteristic control parts extended from the wiring layer into the interlayer dielectric layer. The bottom of the one or more wiring characteristic control parts may be positioned at a higher level than the bottom of the interlayer dielectric layer.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventor: Wang Su KIM
  • Publication number: 20150130069
    Abstract: A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Ankit Mahajan, Carl Daniel Frisbie, Lorraine F. Francis
  • Publication number: 20150130067
    Abstract: This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate. The present invention also provides a semiconductor device having the ohmic contact structure.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Wei Chiu, Ting-Wei Liao, Chieh-Hsiung Kuan, Tsung-Yi Huang, Tsung-Yu Yang
  • Patent number: 9030019
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer
  • Patent number: 9030011
    Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Xintec Inc.
    Inventors: Chao-Yen Lin, Yi-Hang Lin
  • Patent number: 9029997
    Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N?1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho Cheol Lee
  • Patent number: 9030017
    Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9030020
    Abstract: In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: May 12, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiko Kato, Hidenobu Nagashima
  • Patent number: 9030023
    Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Jing Wang, Lin Lin, Qiuling Jia, Qi Yang, Jianxin Liu