Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Abstract: A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Abstract: When a voltage is applied to a semiconductor element formed into a semiconductor substrate for evaluating the electrical characteristic of the semiconductor element, partial discharge between the semiconductor element and an inter-element portion, adhesion of a foreign substance to the semiconductor substrate, and formation of a trace of a component in the semiconductor substrate are prevented. A semiconductor device includes a semiconductor substrate and a discharge inhibitor. The semiconductor substrate includes a plurality of semiconductor elements and an inter-element portion. The semiconductor elements are arranged in a spreading direction of the semiconductor substrate. The inter-element portion is between adjacent semiconductor elements among the semiconductor elements. The discharge inhibitor is bonded not to a surface of a center of each semiconductor element among the semiconductor elements but to a surface of the inter-element portion. The discharge inhibitor is made of an insulator.

Abstract: There is provided a solid-state image-capturing element capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: According to one embodiment, a magnetic memory device includes first and second wirings, and memory cells between the first and second wirings, and each including a switching element and a magnetoresistance effect element, the switching element being connected to a first wiring, and the magnetoresistance effect element being connected to a second wiring. The switching element includes a bottom electrode, a top electrode, and a switching material layer between the bottom and top electrodes, and the bottom electrode included in each of the memory cells adjacent to each other in a first direction is continuously provided on the first wiring connecting the memory cells adjacent to each other in the first direction.

Abstract: Technologies relating to crossbar array circuits with proton-based two-terminal volatile memristive devices are disclosed. An example apparatus includes a first bottom conductive layer, a capacitor oxide layer formed on the first bottom conductive layer, a second bottom conductive layer formed on the capacitor oxide layer, a second oxide layer formed on the second bottom conductive layer, and a proton reservoir layer formed on the second oxide layer. In some embodiments, the second bottom conductive layer is H-doped. In some embodiments, a conductance of the second oxide layer is modulated by H-dopant.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

Abstract: Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells.

Abstract: A semiconductor device includes a first metal wiring pattern area, and a second metal wiring pattern area that does not overlap the first metal wiring pattern area in a plan view. The first metal wiring pattern area includes a first pattern, the second metal wiring pattern area includes a second pattern that is spaced apart from the first pattern and includes one or more lines. The first metal wiring pattern area includes an assist pattern comprising one or more lines. The assist pattern is spaced apart from the second pattern, parallel with the second pattern, and is between the first pattern and the second pattern. One end of the assist pattern is connected to the first pattern.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A stretchable wiring board that includes: a stretchable substrate; a first wiring line on the stretchable substrate; an insulating layer overlapping a first part of the first wiring line in a plan view of the stretchable wiring board; and a second wiring line overlapping the first part of the first wiring line in the plan view with the insulating layer interposed therebetween. The insulating layer has at least one first notch, and in the plan view, the at least one first notch does not overlap the first wiring line and overlaps the second wiring line.

Abstract: Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

Abstract: The present disclosure provides a manufacturing method of a memory structure. The manufacturing method includes the operations of: receiving a substrate; forming a landing pad layer in the substrate; forming trenches over the landing pad layer; and forming a top pad over the trenches to form the capacitor array. The operation of forming the trenches over the landing pad layer includes the operations of: forming an integrated layer having an array pattern over the landing pad layer; forming, by a chop mask, a masking layer to mask an edge portion of the array pattern so as to define a rectangle portion of the array pattern; and etching the integrated layer according to the rectangle portion of the array pattern to form the plurality of trenches. The edge portion of the array pattern surrounds the rectangle portion of the array pattern.

Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.

Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

Abstract: Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

Abstract: A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area.

Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

Abstract: Disclosed is a display apparatus. The display apparatus includes a substrate, a first wiring part on the substrate, a first insulation layer on the first wiring part, a microchip on the first insulation layer, a second wiring part on the microchip, and an organic light emitting device on the second wiring part. The microchip includes a first surface and a second surface opposite to each other, a first pad part on the first surface, and a second pad part on the second surface. The first pad part is connected to the first wiring part, and the second pad part is connected to the second wiring part.

Abstract: A semiconductor device includes a substrate, an active region and an inactive region surrounding the active region, a gate electrode, a drain electrode and a source electrode on the active region, a drain interconnection including a drain finger and a drain bar, and a source interconnection including a source finger and a source bar. The source bar is located on an opposite side of the drain bar across the active region in a first direction. The source electrode includes a first side facing the drain bar in the first direction and a first depression in a middle of the first side. A first depth of the first depression in the first direction is equal or more than a first interval between the drain bar and the first side in the first direction.

Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Abstract: A sensor component having a MEMS sensor and an ASIC for one sensor function each. A base element, a wall element in the form of a frame and a cover together enclose a cavity of a housing. The MEMS sensor is mounted inside the cavity on the base element of the housing. The ASIC has an active sensor surface and is mounted on or under the cover or is embedded in the cover. Electrical external contacts for the MEMS sensor and ASIC are provided on an external surface of the housing. The cavity has at least one opening or bushing.

Abstract: Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.

Abstract: A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: Disclosed herein is an organic light emitting diode display, including a substrate, a first thin film transistor including a first active pattern on the substrate and a first gate electrode on the first active pattern, a data wire on the first gate electrode, a first interlayer insulating layer between the first gate electrode and the data wire, a second interlayer insulating layer positioned the first interlayer insulating layer and the data wire, and an organic light emitting diode positioned on the data wire and connected to the first active pattern.

Abstract: A thermoelectric device including: a thermoelectric material layer comprising a thermoelectric material; a transition layer on the thermoelectric material; and a diffusion prevention layer on the transition layer, wherein the thermoelectric material comprises a compound of Formula 1: (A1-aA?a)4-x(B1-bB?b)3-y-zCz??Formula 1 wherein A and A? are different from each other, A is a Group 13 element, and A? is at least one element of a Group 13 element, a Group 14 element, a rare-earth element, or a transition metal, B and B? are different from each other, B is a Group 16 element, and B? is at least one element of a Group 14 element, a Group 15 element, or a Group 16 element, C is at least one halogen atom, a complies with the inequality 0?a<1, b complies with the inequality 0?b<1, x complies with the inequality ?1<x<1, y complies with the inequality ?1<y<1, and z complies with 0?z<0.5.

Abstract: A method for manufacturing an optical member includes providing a silicon substrate having a first main surface of a {110} plane and a second main surface of a {110} plane that are parallel to each other, forming mask patterns on the first main surface and the second main surface, each of the mask patterns having an opening extending in one direction, so that the opening on a first main surface side and the opening on a second main surface side are disposed alternately, or so that the opening on the second main surface side are disposed directly under the opening on the first main surface side, forming recesses having sloped surfaces in the first main surface side and the second main surface side by wet etching the silicon substrate using the mask patterns as masks, and forming a reflective film on the first main surface or the second main surface.

Abstract: The present invention discloses a light-emitting device and the manufacturing method thereof. The light-emitting device comprises: a substrate including a protrusion part and a base part; a lattice buffer layer formed on the substrate and including a first region substantially right above the protrusion part and a second region substantially right above the base part, wherein the first region includes a recess therein; a light-emitting stack formed on the lattice buffer layer and the recess; and electrodes formed on and electrically connected to the light-emitting stack.

Abstract: A stretchable board includes: a base material having stretchability; first and second electronic components mounted on the base material; a wire arranged on the base material; and first and second connectors for connecting the first and second electronic components and the wire to each other. At least a portion of the first electronic component and at least a portion of the second electronic component face each other in a planned stretching direction in which the base material includes: a facing zone interposed between the first and second electronic components in a planned stretching direction and a non-facing zone other than the facing zone on the base material, in which at least a portion of the first connector or at least a portion of the second connector are arranged in the non-facing zone, and in which at least one of the wires is arranged in the non-facing zone.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: A magnetic core inductor chip includes a core and a coil. The core is in the form of a single piece of a magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. Methods for making the magnetic core inductor chip are also disclosed.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: According to one embodiment, the p-side electrode is provided on the second semiconductor layer. The insulating film is provided on the p-side electrode. The n-side electrode includes a first portion, a second portion, and a third portion. The first portion is provided on a side face of the first semiconductor layer. The second portion is provided in the first n-side region. The third portion overlaps the p-side electrode via the insulating film and connects the first portion and the second portion to each other.

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

Abstract: A disclosed circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, first and second cross wires attached to the substrate and disposed proximate the electronic device, and one or more wire segments attached to the substrate. The one or more wire segments have first and second portions attached at a third portion of the first cross wire and at a fourth portion of the second cross wire, respectively. The first and second cross wires and the one or more wire segments are round wires having round cross sections. The first portion and the third portion have flat areas of contact, and the second and fourth portions have flat areas of contact. A first bond wire is connected to the electronic device and to the first portion of the one or more wire segments, and a second bond wire is connected to the electronic device and to the second portion of the one or more wire segments.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.