Cross-over Arrangement, Component Or Structure Patents (Class 257/776)
  • Patent number: 11569808
    Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 31, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tuli Luthuli Dake, Satish Kumar Vemuri, Ritesh Jitendra Oza, Laszlo Balogh
  • Patent number: 11557552
    Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Chin Lee Kuan, Jackson Chung Peng Kong, Bok Eng Cheah
  • Patent number: 11411006
    Abstract: The present disclosure provides a manufacturing method of a memory structure. The manufacturing method includes the operations of: receiving a substrate; forming a landing pad layer in the substrate; forming trenches over the landing pad layer; and forming a top pad over the trenches to form the capacitor array. The operation of forming the trenches over the landing pad layer includes the operations of: forming an integrated layer having an array pattern over the landing pad layer; forming, by a chop mask, a masking layer to mask an edge portion of the array pattern so as to define a rectangle portion of the array pattern; and etching the integrated layer according to the rectangle portion of the array pattern to form the plurality of trenches. The edge portion of the array pattern surrounds the rectangle portion of the array pattern.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 9, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Ting Lin, Pei-Jhen Wu
  • Patent number: 11328994
    Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 10, 2022
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 11276626
    Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 15, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Shintaro Shinjo, Koji Yamanaka
  • Patent number: 11121181
    Abstract: Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Ahmed Nayaz Noemaun
  • Patent number: 11004491
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anuj Gupta, Bipul C. Paul, Joseph Versaggi
  • Patent number: 10985137
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen Hsin Wei
  • Patent number: 10985233
    Abstract: A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: April 20, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kinyeng Kang, Taewoo Kim, Taehoon Yang, Seunghwan Cho, Jonghyun Choi
  • Patent number: 10910455
    Abstract: Disclosed is a display apparatus. The display apparatus includes a substrate, a first wiring part on the substrate, a first insulation layer on the first wiring part, a microchip on the first insulation layer, a second wiring part on the microchip, and an organic light emitting device on the second wiring part. The microchip includes a first surface and a second surface opposite to each other, a first pad part on the first surface, and a second pad part on the second surface. The first pad part is connected to the first wiring part, and the second pad part is connected to the second wiring part.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: February 2, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Haejin Park, Kimin Son
  • Patent number: 10903323
    Abstract: A semiconductor device includes a substrate, an active region and an inactive region surrounding the active region, a gate electrode, a drain electrode and a source electrode on the active region, a drain interconnection including a drain finger and a drain bar, and a source interconnection including a source finger and a source bar. The source bar is located on an opposite side of the drain bar across the active region in a first direction. The source electrode includes a first side facing the drain bar in the first direction and a first depression in a middle of the first side. A first depth of the first depression in the first direction is equal or more than a first interval between the drain bar and the first side in the first direction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 26, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Chihoko Akiyama
  • Patent number: 10686015
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 10600884
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Patent number: 10544035
    Abstract: A sensor component having a MEMS sensor and an ASIC for one sensor function each. A base element, a wall element in the form of a frame and a cover together enclose a cavity of a housing. The MEMS sensor is mounted inside the cavity on the base element of the housing. The ASIC has an active sensor surface and is mounted on or under the cover or is embedded in the cover. Electrical external contacts for the MEMS sensor and ASIC are provided on an external surface of the housing. The cavity has at least one opening or bushing.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 28, 2020
    Assignee: TDK Corporation
    Inventor: Wolfgang Pahl
  • Patent number: 10510407
    Abstract: Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10497684
    Abstract: A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Wissen, Daniel Domes, Andreas Groove
  • Patent number: 10483159
    Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chen Chu, Tai-I Yang, Cheng-Chi Chuang, Chia-Tien Wu
  • Patent number: 10453908
    Abstract: Disclosed herein is an organic light emitting diode display, including a substrate, a first thin film transistor including a first active pattern on the substrate and a first gate electrode on the first active pattern, a data wire on the first gate electrode, a first interlayer insulating layer between the first gate electrode and the data wire, a second interlayer insulating layer positioned the first interlayer insulating layer and the data wire, and an organic light emitting diode positioned on the data wire and connected to the first active pattern.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Woo Park, Wang Woo Lee
  • Patent number: 10326068
    Abstract: A thermoelectric device including: a thermoelectric material layer comprising a thermoelectric material; a transition layer on the thermoelectric material; and a diffusion prevention layer on the transition layer, wherein the thermoelectric material comprises a compound of Formula 1: (A1-aA?a)4-x(B1-bB?b)3-y-zCz??Formula 1 wherein A and A? are different from each other, A is a Group 13 element, and A? is at least one element of a Group 13 element, a Group 14 element, a rare-earth element, or a transition metal, B and B? are different from each other, B is a Group 16 element, and B? is at least one element of a Group 14 element, a Group 15 element, or a Group 16 element, C is at least one halogen atom, a complies with the inequality 0?a<1, b complies with the inequality 0?b<1, x complies with the inequality ?1<x<1, y complies with the inequality ?1<y<1, and z complies with 0?z<0.5.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-il Kim, Sung-woo Hwang, Sang-mock Lee, Kyu-hyoung Lee, Vilius Mykhailovsky, Roman Mochernyuk
  • Patent number: 10320144
    Abstract: A method for manufacturing an optical member includes providing a silicon substrate having a first main surface of a {110} plane and a second main surface of a {110} plane that are parallel to each other, forming mask patterns on the first main surface and the second main surface, each of the mask patterns having an opening extending in one direction, so that the opening on a first main surface side and the opening on a second main surface side are disposed alternately, or so that the opening on the second main surface side are disposed directly under the opening on the first main surface side, forming recesses having sloped surfaces in the first main surface side and the second main surface side by wet etching the silicon substrate using the mask patterns as masks, and forming a reflective film on the first main surface or the second main surface.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 11, 2019
    Assignee: NICHI CORPORATION
    Inventor: Shingo Tanisaka
  • Patent number: 10304993
    Abstract: The present invention discloses a light-emitting device and the manufacturing method thereof. The light-emitting device comprises: a substrate including a protrusion part and a base part; a lattice buffer layer formed on the substrate and including a first region substantially right above the protrusion part and a second region substantially right above the base part, wherein the first region includes a recess therein; a light-emitting stack formed on the lattice buffer layer and the recess; and electrodes formed on and electrically connected to the light-emitting stack.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 28, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Yung-Hsiang Lin, Wei-Chih Peng
  • Patent number: 10306755
    Abstract: A stretchable board includes: a base material having stretchability; first and second electronic components mounted on the base material; a wire arranged on the base material; and first and second connectors for connecting the first and second electronic components and the wire to each other. At least a portion of the first electronic component and at least a portion of the second electronic component face each other in a planned stretching direction in which the base material includes: a facing zone interposed between the first and second electronic components in a planned stretching direction and a non-facing zone other than the facing zone on the base material, in which at least a portion of the first connector or at least a portion of the second connector are arranged in the non-facing zone, and in which at least one of the wires is arranged in the non-facing zone.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 28, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Shingo Ogura, Tetsu Hammura
  • Patent number: 10204878
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 10181378
    Abstract: A magnetic core inductor chip includes a core and a coil. The core is in the form of a single piece of a magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. Methods for making the magnetic core inductor chip are also disclosed.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 15, 2019
    Assignee: WAFER MEMS CO., LTD
    Inventors: Min-Ho Hsiao, Pang-Yen Lee, Yen-Hao Tseng
  • Patent number: 10056336
    Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masami Koketsu, Toshiaki Sawada
  • Patent number: 10014710
    Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Mark A. Schaecher, Teong Guan Yew, Eng Huat Goh
  • Patent number: 9911713
    Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 6, 2018
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Markus Wimplinger
  • Patent number: 9818664
    Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 14, 2017
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Patent number: 9748191
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 29, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 9722143
    Abstract: According to one embodiment, the p-side electrode is provided on the second semiconductor layer. The insulating film is provided on the p-side electrode. The n-side electrode includes a first portion, a second portion, and a third portion. The first portion is provided on a side face of the first semiconductor layer. The second portion is provided in the first n-side region. The third portion overlaps the p-side electrode via the insulating film and connects the first portion and the second portion to each other.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideto Furuyama, Yoshiaki Sugizaki
  • Patent number: 9691704
    Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Chia-Chang Hsu, Nien-Ting Ho, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun-Tzu Chang, Yang-Ju Lu, Wei-Ming Hsiao, Wei-Ning Chen
  • Patent number: 9607888
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Patent number: 9565752
    Abstract: A disclosed circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, first and second cross wires attached to the substrate and disposed proximate the electronic device, and one or more wire segments attached to the substrate. The one or more wire segments have first and second portions attached at a third portion of the first cross wire and at a fourth portion of the second cross wire, respectively. The first and second cross wires and the one or more wire segments are round wires having round cross sections. The first portion and the third portion have flat areas of contact, and the second and fourth portions have flat areas of contact. A first bond wire is connected to the electronic device and to the first portion of the one or more wire segments, and a second bond wire is connected to the electronic device and to the second portion of the one or more wire segments.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: February 7, 2017
    Assignee: Automated Assembly Corporation
    Inventors: Robert Neuman, Scott Lindblad
  • Patent number: 9508630
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 9484287
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: November 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 9484286
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: November 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 9418936
    Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 16, 2016
    Assignee: SK hynix Inc.
    Inventors: Jae Hwan Kim, Won John Choi
  • Patent number: 9355950
    Abstract: A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer. The power semiconductor module further includes a first interconnect attached to the first terminal, a second interconnect attached to the second terminal and a flexible board including a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another. The first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 9343381
    Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Uwe Schmalzbauer, Rudolf Zelsacher
  • Patent number: 9305879
    Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 9246026
    Abstract: Disclosed is a solar cell having a collecting electrode on one main surface of a photoelectric conversion section. The collecting electrode includes a first electroconductive layer and a second electroconductive layer in this order from the photoelectric conversion section side, and further includes an insulating layer between the first electroconductive layer and the second electroconductive layer. The first electroconductive layer includes a low-melting-point material, and a part of the second electroconductive layer is conductively connected with the first electroconductive layer through, for example, an opening in the insulating layer. The second electrode layer is preferably formed by a plating method. In addition, it is preferable that before forming the second electroconductive layer, annealing by heating is carried out to generate the opening section in the insulating layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 26, 2016
    Assignee: KANEKA CORPORATION
    Inventors: Daisuke Adachi, Kenji Yamamoto, Jose Luis Hernandez, Nick Valckx
  • Patent number: 9230906
    Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Schulz, Sergei Postnikov
  • Patent number: 9224868
    Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.
    Type: Grant
    Filed: February 15, 2015
    Date of Patent: December 29, 2015
    Assignee: AU Optronics Corp.
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Patent number: 9196570
    Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kiyotada Funane
  • Patent number: 9184111
    Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 10, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yen Lee, Chi-Cheng Lin, Hsin-Chang Tsai
  • Patent number: 9166001
    Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
  • Patent number: 9142527
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 22, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Patent number: 9136205
    Abstract: A semiconductor device includes a semiconductor layer, an active region defined in the semiconductor layer, first fingers provided on the active region and arranged in parallel with respect to a first direction, second fingers provided on the active region and interleaved with the first fingers, a bus line that is provided on an outside of the active region and interconnects the first fingers, first air bridges that are provided on the outside of the active region and are extended over the bus line, and that are connected to the second fingers, and second air bridges that are provided on the outside of the active region and are arranged in a second direction which crosses to the first direction, and that interconnect the first air bridges.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 15, 2015
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tadayuki Shimura
  • Patent number: 9117831
    Abstract: A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 25, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Jung Yang, Yu-Wen Liu, Michael Shou-Ming Tong, Hsien-Wei Chen, Chung-Ying Yang, Tsung-Yuan Yu
  • Patent number: 9093299
    Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wen Liu, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Hsiao-Chiu Hsu, Hsin-Ying Lin