Cross-over Arrangement, Component Or Structure Patents (Class 257/776)
  • Patent number: 9418936
    Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 16, 2016
    Assignee: SK hynix Inc.
    Inventors: Jae Hwan Kim, Won John Choi
  • Patent number: 9355950
    Abstract: A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer. The power semiconductor module further includes a first interconnect attached to the first terminal, a second interconnect attached to the second terminal and a flexible board including a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another. The first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 9343381
    Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Uwe Schmalzbauer, Rudolf Zelsacher
  • Patent number: 9305879
    Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 9246026
    Abstract: Disclosed is a solar cell having a collecting electrode on one main surface of a photoelectric conversion section. The collecting electrode includes a first electroconductive layer and a second electroconductive layer in this order from the photoelectric conversion section side, and further includes an insulating layer between the first electroconductive layer and the second electroconductive layer. The first electroconductive layer includes a low-melting-point material, and a part of the second electroconductive layer is conductively connected with the first electroconductive layer through, for example, an opening in the insulating layer. The second electrode layer is preferably formed by a plating method. In addition, it is preferable that before forming the second electroconductive layer, annealing by heating is carried out to generate the opening section in the insulating layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 26, 2016
    Assignee: KANEKA CORPORATION
    Inventors: Daisuke Adachi, Kenji Yamamoto, Jose Luis Hernandez, Nick Valckx
  • Patent number: 9230906
    Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Schulz, Sergei Postnikov
  • Patent number: 9224868
    Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.
    Type: Grant
    Filed: February 15, 2015
    Date of Patent: December 29, 2015
    Assignee: AU Optronics Corp.
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Patent number: 9196570
    Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kiyotada Funane
  • Patent number: 9184111
    Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 10, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yen Lee, Chi-Cheng Lin, Hsin-Chang Tsai
  • Patent number: 9166001
    Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
  • Patent number: 9142527
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 22, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Patent number: 9136205
    Abstract: A semiconductor device includes a semiconductor layer, an active region defined in the semiconductor layer, first fingers provided on the active region and arranged in parallel with respect to a first direction, second fingers provided on the active region and interleaved with the first fingers, a bus line that is provided on an outside of the active region and interconnects the first fingers, first air bridges that are provided on the outside of the active region and are extended over the bus line, and that are connected to the second fingers, and second air bridges that are provided on the outside of the active region and are arranged in a second direction which crosses to the first direction, and that interconnect the first air bridges.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 15, 2015
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tadayuki Shimura
  • Patent number: 9117831
    Abstract: A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 25, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Jung Yang, Yu-Wen Liu, Michael Shou-Ming Tong, Hsien-Wei Chen, Chung-Ying Yang, Tsung-Yuan Yu
  • Patent number: 9093299
    Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wen Liu, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Hsiao-Chiu Hsu, Hsin-Ying Lin
  • Patent number: 9035461
    Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 9030019
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer
  • Patent number: 9024450
    Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 9018771
    Abstract: A thin film apparatus having a plurality of thin film cells is disclosed. Each thin film cell includes a crystalline layer and a surrounding layer. The crystalline layer has a shape of polygon. The surrounding layer is partially located on the crystalline layer. The crystalline layer is surrounded by the surrounding layer.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 28, 2015
    Assignee: Sensor Tek Co., Ltd.
    Inventors: Po-Wei Lu, Mao-Chen Liu, Wen-Chieh Chou, Chun-Chieh Wang, Shu-Yi Weng
  • Publication number: 20150102504
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Application
    Filed: September 24, 2014
    Publication date: April 16, 2015
    Inventors: Je-min PARK, Dae-ik KIM
  • Patent number: 9000584
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Patent number: 8993429
    Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 31, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8981573
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8981572
    Abstract: To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 17, 2015
    Inventors: Won Chul Do, Yong Jae Ko
  • Publication number: 20150069630
    Abstract: Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Samuele Sciarrillo
  • Patent number: 8975739
    Abstract: The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Xintec Inc.
    Inventor: Ming-Chung Chung
  • Patent number: 8970001
    Abstract: A structure includes a metal feature, and a passivation layer having a portion overlapping the metal feature. The passivation layer includes a non-low-k dielectric material. A polymer layer is over the passivation layer. A Post-Passivation Interconnect (PPI) extends into the polymer layer to electrically couple to the metal feature. A guard ring includes a second PPI, wherein the guard ring is electrically grounded. The second PPI substantially encircles the first PPI.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • Patent number: 8958229
    Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Won Kim
  • Patent number: 8952500
    Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8946873
    Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 8940634
    Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: January 27, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Patent number: 8933343
    Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Ming-Fung Hsieh, Yu-Chia Chang, Chun-Pin Huang, Yung-Chang Peng
  • Patent number: 8912655
    Abstract: When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shingo Nakajima
  • Patent number: 8907497
    Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8901728
    Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Publication number: 20140346682
    Abstract: A semiconductor device includes a plurality of first conductive layers stacked on top of one another, a plurality of first slits passing through the first conductive layers, and a plurality of second slits passing through the first conductive layers and crossing end portions of the first slits to form cross-shaped edges.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 27, 2014
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, Yong Hyun LIM
  • Patent number: 8890314
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Transphorm, Inc.
    Inventor: Yifeng Wu
  • Patent number: 8890607
    Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8890327
    Abstract: A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 18, 2014
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 8883642
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakana Kai, Tomonori Aoyama
  • Patent number: 8884439
    Abstract: Disclosed herein is a joining electrode including: an insulating layer; a recessed portion formed in the insulating layer; a covering layer formed on a side surface and a bottom surface of the recessed portion; and a joining metallic layer formed on the covering layer and having an upper surface protruding from a surface of the insulating layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventor: Kenichi Aoyagi
  • Patent number: 8884438
    Abstract: Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Larry E. Mosley
  • Patent number: 8884444
    Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nitta
  • Publication number: 20140327153
    Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: GLOBALFOUNDRIES INC.
  • Publication number: 20140327154
    Abstract: A micromechanical component having a substrate, a micromechanical functional layer situated above the substrate, and an encapsulation layer situated above the functional layer, and a method for producing the micromechanical component are provided, the encapsulation layer having at least one trench, and a bridging of the trench by at least one electrically insulating connection link is provided.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Applicant: ROBERT BOSCH GMBH
    Inventors: Volker SCHMITZ, Axel GROSSE
  • Patent number: 8878365
    Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 8872352
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872340
    Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 8872347
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872353
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe