Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.

Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.

Abstract: Electronic devices and more particularly diamond-based electronic devices and corresponding contact structures are disclosed. Electrical contact structures to diamond layers, including n-type, phosphorus doped single-crystal diamond are disclosed. In particular, electrical contact structures are formed through an arrangement of one or more nanostructured carbon layers with high nitrogen incorporation that are provided between metal contacts and n-type diamond layers in diamond-based electronic devices. Nanostructured carbon layers may be configured to mitigate reduced phosphorus incorporation in n-type diamond layers, thereby providing low specific contact resistances for corresponding devices. Diamond p-i-n diodes for direct electron emission applications are also disclosed that include electrical contact structures with nanostructured carbon layers.

Abstract: In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Abstract: A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate below and adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

Abstract: A method includes a graphene precursor formation process of: heating a SiC substrate to sublimate Si atoms in a Si surface of the SiC substrate so that a graphene precursor is formed; and stopping the heating before the graphene precursor is covered with graphene. A SiC substrate to be treated in the graphene precursor formation process is provided with a step including a plurality of molecular layers. The step has a stepped structure in which a molecular layer whose C atom has two dangling bonds is disposed closer to the surface than a molecular layer whose C atom has one dangling bond.

Abstract: According to one embodiment, a semiconductor device includes a first element region. The first element region includes first, second, and third semiconductor regions, and first, and second conductive layers. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second semiconductor region includes a first semiconductor portion. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction.

Abstract: A self-supporting ultra-fine nanocrystalline diamond thick film, the thickness being 100-3000 microns, wherein 1 nanometer?diamond grain size?20 nanometers. A method for using chemical vapor deposition to grow ultra-fine nanocrystalline diamond on a silicon substrate, and separating the silicon substrate and the diamond to acquire the self-supporting ultra-fine nanocrystalline diamond thick film. The chemical vapor deposition method is simple and effective, and prepares a high-quality ultra-fine nanocrystalline diamond thick film.

Abstract: A semiconductor device includes a semiconductor chip in which a field effect transistor mainly containing GaN is formed on a surface of a SiC semiconductor substrate. The semiconductor device includes a metal base on which a back surface of the semiconductor chip is mounted through a conductive adhesive material containing Ag and a resin mold configured to seal the semiconductor chip. A metal having wettability lower than wettability of Au or Cu with respect to Ag is exposed in a region extending along an edge of the back surface.

Abstract: Photovoltaics configured to be manufactured without epitaxial processes and methods for such manufacture are provided. Methods utilize bulk semiconducting crystal substrates, such as, for example, GaAs and InP such that epitaxy processes are not required. Nanowire etch and exfoliation processes are used allowing the manufacture of large numbers of photovoltaic cells per substrate wafer (e.g., greater than 100). Photovoltaic cells incorporate electron and hole selective contacts such that epitaxial heterojunctions are avoided during manufacture.

Abstract: A semiconductor device of an embodiment includes: a silicon carbide layer including a first silicon carbide region of n-type containing one metal element selected from a group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) and a second silicon carbide region of p-type containing the metal element; and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. Among the metal elements contained in the first silicon carbide region, a proportion of the metal element positioned at a carbon site is higher than a proportion of the metal element positioned at an interstitial position. Among the metal elements contained in the second silicon carbide region, a proportion of the metal element positioned at an interstitial position is higher than a proportion of the metal element positioned at a carbon site.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer including first and second trenches, a first silicon carbide region of n-type, a second silicon carbide region of p-type disposed between the first trench and the second trench and having a depth deeper than depths of the first and second trenches, and a third silicon carbide region of n-type on the second silicon carbide region, a first gate electrode, a second gate electrode. The second silicon carbide region includes a first region of which a depth becomes deeper toward the second trench, and a second region of which a depth becomes deeper toward the first trench. In the second silicon carbide region, a first concentration distribution of a p-type impurity has a first concentration peak at a first position, and has a second concentration peak at a second position closer to the second trench than the first position.

Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.

Abstract: Provided is a single crystal diamond having a lowered dislocation density. The single crystal diamond (10) is provided with single crystal diamond layers (2, 3). One single crystal diamond layer (2) is formed on a diamond substrate (1) and contains point defects. The other single crystal diamond layer (3) is grown on the single crystal diamond layer (2). The single crystal diamond layers (2, 3) have a lower dislocation density than the diamond substrate.

Abstract: A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

Abstract: A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.

Abstract: Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion partitioned from a second portion. A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion partitioned from a second portion. The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.

Abstract: An image sensor is disclosed. The image sensor includes a substrate including an active region and a dummy region, a plurality of unit pixels on the active region, a transparent conductive layer on a first surface of the substrate, a light-blocking layer on the transparent conductive layer and electrically connected to the transparent conductive layer, the light-blocking layer having a grid structure adjacent light transmission regions, and a pad electrically connected to the light-blocking layer, on the dummy region.

Abstract: An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having a first region and a second region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a barrier layer disposed on the semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode disposed therebetween, which are disposed on the barrier layer in the first region, a second source electrode, a second drain electrode, and a second gate electrode disposed therebetween, which are disposed on the barrier layer in the second region, and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure over a substrate, and a second fin structure over the substrate. The FinFET device structure also includes a first isolation structure over the substrate and surrounding the first fin structure. The first fin structure is protruded from a top surface of the first isolation structure. The FinFET device structure further includes a second isolation structure over the substrate and surrounding the second fin structure. The second fin structure is protruded from a top surface of the second isolation structure, and the first fin structure has a vertical sidewall surface and the second fin structure has a sloped sidewall surface.

Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a base substrate including a first region, a second region and a third region between the first and the second region; forming a dummy gate structure extending from the first region to the second region and through the third region; forming first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region; forming second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region; forming an opening in the dummy gate structure in the third region and exposing the base substrate in the third region; and forming an interlayer dielectric layer within the opening to have a top surface coplanar with the dummy gate structure.

Abstract: This disclosure relates to a semiconductor device and corresponding method of manufacturing the semiconductor device. The semiconductor device includes a MOS transistor device die and a SiGe diode. The SiGe diode is integrally arranged on the MOS transistor device die, so that the SiGe diode is electrically connected between a source connection and drain connection of the MOS transistor device die.

Abstract: A semiconductor device having, in a plan view, a termination region surrounding an active region. The semiconductor device includes a semiconductor substrate containing silicon carbide, a first-conductivity-type region provided in the semiconductor substrate at its first main surface, a plurality of first second-conductivity-type regions selectively formed in the semiconductor substrate at its first main surface, a plurality of silicide films respectively in ohmic contact with the first second-conductivity-type regions, a first electrode that is in contact with the silicide films to form ohmic regions, with the first second-conductivity-type regions to form non-operating regions, and with the first-conductivity-type region to form Schottky regions, a second electrode provided at a second main surface of the semiconductor substrate, and a second second-conductivity-type region provided in the termination region.

Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.

Abstract: A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H-SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 2.5 inclusions/cm2, wherein a total density of large pit defects and triangular defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.6 defects/cm2 or less.

Abstract: [Object] To stably form a low-resistance electrical coupling between a metal and a semiconductor. [Solution] An electrical coupling structure includes: a semiconductor layer; a metal layer; and an intermediate layer that is held between the semiconductor layer and the metal layer, and includes an insulating layer provided on the semiconductor layer side and a two-dimensional material layer provided on the metal layer side.

Abstract: A power semiconductor module, as well as a corresponding method of manufacture, are provided. The power semiconductor module has a plurality of power switches. A first subset of the power switches forms part of a first electrical current branch. A second subset of the power switches forms part of a second electrical current branch. Within the current branches, the associated power switches are arranged symmetrically with respect to the DC voltage contacts and are connected in such a way that a current density which is formed in the individual current paths which are respectively assigned to one of the power switches is at least substantially homogeneously distributed during the high frequency operation of the power semiconductor module and/or in the operation of the power switches with high voltage gradients.

Abstract: Techniques are disclosed for using compositionally different contact materials for p-type and n-type source/drain regions on a common substrate. The different contact materials may be within a common source/drain contact trench, or in type-dedicated trenches. A given contact trench may span one or more fins and include one or more source/drain regions on which a corresponding contact structure is to be made. In an embodiment, an isolation structure between p-type and n-type fins is selective to the trench etch and therefore remains intact within the trench after the target source/drain regions have been exposed. In such cases, the isolation structure physically separates n-type source/drain regions from p-type source/drain regions. The contact structures on the different type source/drain regions may be shorted proximate the top of the isolation structure. Numerous material systems can be used for the channel and source/drain regions, including germanium, group III-V materials, and 2-D materials.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.

Abstract: Provided is a technique capable of obtaining sufficient latch-up tolerance and enabling integration. The wide band gap semiconductor device includes: a collector region, a charge storage region having an impurity concentration higher than that of the drift region, a base region, a charge extraction region having an impurity concentration higher than that of the base region, an emitter region, a Schottky electrode, a gate insulating film, a gate electrode, an emitter electrode, and a collector electrode.

Abstract: A semiconductor device includes a SiC body having a first semiconductor area of a first conductivity type and a second semiconductor area of a second conductivity type. The first semiconductor area is electrically contacted with a first surface of the SiC body and forms a pn junction with the second semiconductor area. The first and second semiconductor areas are arranged on one another in a vertical direction perpendicular to the first surface. The first semiconductor area has first and second dopant species. An average dopant concentration of the first dopant species in a first part of the first semiconductor area adjoining the first surface is greater than an average dopant concentration of the second dopant species. An average dopant concentration of the second dopant species in a second part of the first semiconductor area adjoining the second semiconductor area is greater than a dopant concentration of the first dopant species.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 ?m and not more than 200 ?m. The contact angle between the first jutting portion and the first sloped portion is 65° or less.

Abstract: An embodiment is a semiconductor device includes a silicon carbide layer having a first plane and a second plane facing the first plane; a gate electrode; an aluminum nitride layer located between the silicon carbide layer and the gate electrode, the aluminum nitride layer containing an aluminum nitride crystal; a first insulating layer located between the silicon carbide layer and the aluminum nitride layer; and a second insulating layer located between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

Abstract: An embodiment of a semiconductor device including a silicon carbide layer having a first and a second planes; a first silicon carbide region of first conductivity type in the silicon carbide layer; a second silicon carbide region of second conductivity type in the silicon carbide layer between the first silicon carbide region and the first plane; a third silicon carbide region of the first conductivity type in the silicon carbide layer located between the second silicon carbide region and the first plane; a first electrode located on a side of the first plane; a second electrode located on a side of the second plane; a gate electrode; an aluminum nitride layer containing an aluminum nitride crystal between the second silicon carbide region and the gate electrode; and an insulating layer between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: A semiconductor device including a silicon carbide semiconductor substrate having a first-conductivity-type region at its first main surface. The semiconductor device has, at the first main surface, a plurality of first second-conductivity-type regions and a second second-conductivity-type region selectively provided in the first-conductivity-type region, respectively in an active region and a connecting region of the semiconductor device, and an oxide film provided in a termination region of the semiconductor device and having an inner end that faces the active region. A first silicide film is in ohmic contact with the first second-conductivity-type regions. A second silicide film is in contact with the inner end of the oxide film and in ohmic contact with the second second-conductivity-type region. The semiconductor device has a first electrode including a titanium film and a metal electrode film stacked sequentially on the first main surface, and a second electrode provided at a second main surface.

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.

Abstract: The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Abstract: A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: A method of determining whether a silicon-carbide semiconductor device, which has a metal oxide semiconductor (MOS) gate structure and a built-in diode, is a conforming product. The method includes measuring an ON voltage of the silicon carbide semiconductor device, passing a forward current through the built-in diode of the silicon carbide semiconductor device, measuring another ON voltage of the silicon carbide semiconductor device, which is the ON voltage of the silicon carbide semiconductor device after passing the forward current, calculating a rate of change between the ON voltage and the another ON voltage, and determining that the silicon carbide semiconductor device is a conforming product unless the calculated rate of change is less than 3%.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.