Abstract: An electronic device package is disclosed. The electronic device package includes a board on which an electronic device is mounted, a molded portion formed to cover the electronic device on the board, and a conductive layer disposed on a surface of the molded portion and extended in a trench formed on the board.

Abstract: A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Abstract: In a semiconductor apparatus, the apparatus is so arranged as to comprise: a semiconductor device having electrodes and wiring-interconnects on a main surface of a semiconductor chip; a first resin structure member, being placed on a side of the main surface of the semiconductor chip, constituting, in lateral and upward directions of a specific electrode of the semiconductor device, a hollow-body structure between the specific electrode and the first resin structure member; a second resin structure member covering an outer lateral side of the first resin structure member, and having the permittivity smaller than or equal to the permittivity of the first resin structure member; and an insulation film covering an outer lateral side of the second resin structure member, and having moisture permeability lower than that of the second resin structure member.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Abstract: A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

Abstract: A roll electrode is provided with a core, an electrode, a fixing part and a regulating part. The core extends in an axial direction and has a substantially circular outer circumference. The electrode has an expansion coefficient lower than that of the core. The electrode wound into a roll shape on the outer circumference of the core. The fixing part is fixed to an end portion from which the electrode starts being wound around the core. The regulating part regulates the axial movement of the electrode wound into the roll shape with respect to the core.

Abstract: A method of manufacturing a package structure includes the following processes. A carrier is provided. An adhesive layer is formed on the carrier. A die is attached to the carrier through the adhesive layer. An encapsulant is formed over the carrier to laterally encapsulate the die. A polymer material is formed over the carrier along a surface of the adhesive layer, a surface of the encapsulant and a top surface of the die. A first portion of the polymer material directly on an edge of the carrier has a first thickness larger than a second thickness of a second portion of the polymer material directly on the top surface of the die. A redistribution layer is formed to penetrate through the second portion of the polymer layer and electrically connect to the die.

Abstract: A housing assembly includes a housing, a printed circuit board (PCB) contained in a housing, and a cup-shaped cap having an interior and a flange portion. A tall component extending from the PCB is covered by the cap such that the tall component is disposed in the interior of the cap and the flange portion of the cap engages the PCB. A vacuum is applied and while maintaining the vacuum, an encapsulant is introduced into the housing to a level so as to cover the PCB and certain other components not the relatively taller component(s). When the vacuum is released, a pressure differential between the environmental pressure and the vacuum remaining in the cap interior forces encapsulant into the cap interior to a level higher than that outside of the cap. A multi-level height potting process is achieved.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.

Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.

Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.

Abstract: A package which comprises a carrier, a transducer mounted on the carrier and configured for converting between a package-external property and an electric signal, a package housing at least partially housing at least one of the carrier and the transducer, and a sealing which forms at least part of the package housing for sealing between the package and a package-external body.

Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.

Abstract: One example provides a circuit structure comprising a liquid metal conductive path enclosed in an encapsulant, a polymer circuit support comprising a polymer having a functional species available for a condensation reaction, and a cross-linking agent covalently bonding the encapsulant to the polymer circuit support via the functional species.

Abstract: A device includes a printed circuit board assembly having a printed circuit board and one or more electronic components disposed on the printed circuit board, and a nanofilm disposed on the printed circuit board assembly. The nanofilm includes an inner coating in contact with the printed circuit board assembly, the inner coating including metal oxide nanoparticles having a particle diameter in a range of 5 nm to 100 nm; and an outer coating in contact with the inner coating, the outer coating including silicon dioxide nanoparticles having a particle diameter in a range of 0.1 nm to 10 nm.

Abstract: An electronic product including a supporting structure, a first thermo-formable film, a conductive circuit and a protection layer is provided. The conductive circuit is formed on the first thermo-formable film, and an electronic component is mounted on the conductive circuit. The protection layer covers the electronic component, and includes a second thermo-formable film. The conductive circuit and the electronic component are enclosed between the first thermo-formable film and the second thermo-formable film, and the supporting structure, the first thermo-formable film and the protection layer are bonded and stacked to each other.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area configured to display an image and a peripheral area surrounding the display area. The display device also includes a plurality of signal lines provided in the display area, an encapsulation layer provided over the signal lines and a pad portion provided in the peripheral area. The display device further includes a plurality of connection wires connecting the signal lines and the pad portion, wherein each of the connection wires includes a first portion provided in the peripheral area and a second portion provided in the display area. A portion of the encapsulation layer provided on the display area extends to the peripheral area and placed over the first portions of the connection wires.

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

Abstract: The present disclosure discloses a flexible base substrate, a display substrate and methods of manufacturing the same, and a display device. A groove is provided in a surface of the flexible base substrate, the surface of the flexible base substrate having the groove is provided with a water-oxygen barrier film, and the thickness of the water-oxygen barrier film is smaller than the depth of the groove.

Abstract: Provided is a pressure sensor including a substrate having a cavity therein, a partition wall disposed in the substrate to surround the cavity, a substrate insulation layer disposed on the top surface of the substrate to cover the cavity, a sensing unit disposed on the substrate insulation layer, and an encapsulation layer disposed on the substrate insulation layer to cover the sensing unit. The cavity may extend from a top surface toward a bottom surface of the substrate, the partition wall may have an inner sidewall exposed by the cavity, and at least a portion of the sensing unit may overlap the cavity when viewed in a plan view.

Abstract: An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: The disclosed technology generally relates to sensors comprising a two-dimensional electron gas (2DEG), and more particularly to an AlGaN/GaN 2DEG-based sensor for sensing signals associated with electrocardiograms, and methods of using the same. In one aspect, a sensor comprises a substrate and a GaN/AlGaN hetero-junction structure formed on the substrate and configured to form a two-dimensional electron gas (2DEG) channel within the GaN/AlGaN hetero-junction structure. The sensor additionally comprises Ohmic contacts connected to electrical metallizations and to the 2DEG channel, wherein the GaN/AlGaN hetero-junction structure has a recess formed between the Ohmic contacts. The sensor further comprises a dielectric layer formed on a top surface of the sensor.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.

Abstract: A light emitting module includes: a first substrate including a resin having insulation properties, and a copper component embedded in the resin; a second substrate placed above the copper component of the first substrate, and soldered to the copper component; a mounting electrode formed above the second substrate; and an LED placed above the second substrate, and gold-tin soldered to the mounting electrode.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

Abstract: According to one embodiment, an electrical component comprises a substrate, a functional element formed on the substrate, a first layer which includes through holes, and forms a cavity that stores the functional element on the substrate, and a second layer which is formed on the first layer, and closes the through holes. The first layer includes a first film, a second film on the first film, and a third film on the second film. A Young's modulus of the second film is higher than a Young's modulus of the first film and the third film.

Abstract: A electronic device includes: a circuit board; a semiconductor device, disposed on the circuit board; a cover material, disposed above the semiconductor device; a plurality of bonding wires, respectively connected between a plurality of first contact pads of the semiconductor device and a plurality of second contact pads of the circuit board; a first encapsulant, formed by a first material, arranged to encapsulate a plurality of second bonds formed by electrically connecting the bonding wires to the second contact pads; and a second encapsulant, formed by a second material that is different from the first material, arranged to encapsulate a plurality of first bonds formed by electrically connecting the bonding wires to the first contact pads.

Abstract: A semiconductor device package is assembled using a jig that alters the shape of gel material disposed in a cavity in the package. In one embodiment, a jig having a concave bottom surface is inserted onto uncured gel material disposed within a cavity in a housing of the package to change a top surface of the gel from having a concave shape to a convex shape. The gel is then cured with the jig in place. When the jig is subsequently removed, the cured gel retains the convex shape, which helps to avoid any bond wires from being exposed. The re-shaped gel material reduces internal stresses during thermal cycling and can therefore reduce permanent damage to the package otherwise resulting from such thermal cycling.

Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.

Abstract: An organic light emitting diode display includes a flexible substrate, an organic light emitting diode disposed over the flexible substrate, and an encapsulation film disposed over the flexible substrate to encapsulate the organic light emitting diode, with the organic light emitting diode interposed between the encapsulation film and the flexible substrate. A thermal conduction layer contacts the flexible substrate, wherein the thermal conduction layer faces the organic light emitting diode and the flexible substrate is interposed between the thermal conduction layer and the organic light emitting diode. A first film is disposed over the encapsulation film, and a second film is disposed over the thermal conduction layer.

Abstract: A chemical vapor deposited film includes silicon atoms, oxygen atoms, carbon atoms, and hydrogen atoms. The chemical vapor deposited film is formed by a plasma CVD method such that the concentration of the oxygen atoms is 10-35% by element.

Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract: A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate.

Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.

Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

Abstract: An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically.

Abstract: A method for producing a glass-like layer (3) on a substrate, e.g. a power semiconductor substrate (1), is disclosed. The method comprises the deposition of a glass-like layer vapor-deposited material with plasma-assisted electron beam evaporation. An electronic component can be produced using this method.

Abstract: A display apparatus and a method of manufacturing the same includes a substrate including a plurality of organic layers and a plurality of inorganic layers, a display unit formed on the substrate and an encapsulation unit formed on the display, wherein the plurality of organic layers and the plurality of inorganic layers comprise at least a first organic layer, a first inorganic layer, a second organic layer, and a second inorganic layer which are sequentially stacked, and wherein an interfacial adhesion strength of the second organic layer is higher than an interfacial adhesion strength of the first organic layer.

Abstract: A semiconductor module is provided which is well protected against corrosion and/or other damage which can be caused by moisture and/or other harmful substances surrounding the semiconductor module. A method for producing such a semiconductor module is also provided.