Plural Encapsulating Layers Patents (Class 257/790)
  • Patent number: 10327332
    Abstract: One example provides a circuit structure comprising a liquid metal conductive path enclosed in an encapsulant, a polymer circuit support comprising a polymer having a functional species available for a condensation reaction, and a cross-linking agent covalently bonding the encapsulant to the polymer circuit support via the functional species.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: June 18, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: James David Holbery, Siyuan Ma, Michael David Dickey, Andrew L. Fassler
  • Patent number: 10327338
    Abstract: A device includes a printed circuit board assembly having a printed circuit board and one or more electronic components disposed on the printed circuit board, and a nanofilm disposed on the printed circuit board assembly. The nanofilm includes an inner coating in contact with the printed circuit board assembly, the inner coating including metal oxide nanoparticles having a particle diameter in a range of 5 nm to 100 nm; and an outer coating in contact with the inner coating, the outer coating including silicon dioxide nanoparticles having a particle diameter in a range of 0.1 nm to 10 nm.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 18, 2019
    Assignee: Nanoshield Technology Co., Ltd.
    Inventor: James Cheng Lee
  • Patent number: 10290514
    Abstract: An electronic product including a supporting structure, a first thermo-formable film, a conductive circuit and a protection layer is provided. The conductive circuit is formed on the first thermo-formable film, and an electronic component is mounted on the conductive circuit. The protection layer covers the electronic component, and includes a second thermo-formable film. The conductive circuit and the electronic component are enclosed between the first thermo-formable film and the second thermo-formable film, and the supporting structure, the first thermo-formable film and the protection layer are bonded and stacked to each other.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 14, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yi-Feng Pu, Po-Yu Cheng, Tzu-Shu Lin
  • Patent number: 10204846
    Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area configured to display an image and a peripheral area surrounding the display area. The display device also includes a plurality of signal lines provided in the display area, an encapsulation layer provided over the signal lines and a pad portion provided in the peripheral area. The display device further includes a plurality of connection wires connecting the signal lines and the pad portion, wherein each of the connection wires includes a first portion provided in the peripheral area and a second portion provided in the display area. A portion of the encapsulation layer provided on the display area extends to the peripheral area and placed over the first portions of the connection wires.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nam Jin Kim
  • Patent number: 10177112
    Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Edward Fuergut, Georg Meyer-Berg
  • Patent number: 10121834
    Abstract: The present disclosure discloses a flexible base substrate, a display substrate and methods of manufacturing the same, and a display device. A groove is provided in a surface of the flexible base substrate, the surface of the flexible base substrate having the groove is provided with a water-oxygen barrier film, and the thickness of the water-oxygen barrier film is smaller than the depth of the groove.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: November 6, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mingche Hsieh, Chunyan Xie, Lu Liu, Hejin Wang
  • Patent number: 10113928
    Abstract: Provided is a pressure sensor including a substrate having a cavity therein, a partition wall disposed in the substrate to surround the cavity, a substrate insulation layer disposed on the top surface of the substrate to cover the cavity, a sensing unit disposed on the substrate insulation layer, and an encapsulation layer disposed on the substrate insulation layer to cover the sensing unit. The cavity may extend from a top surface toward a bottom surface of the substrate, the partition wall may have an inner sidewall exposed by the cavity, and at least a portion of the sensing unit may overlap the cavity when viewed in a plan view.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 30, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chang Han Je, Woo Seok Yang, Sung Q Lee, Chang Auck Choi
  • Patent number: 9768136
    Abstract: An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Wei-Yu Chen, Hsuan-Ting Kuo, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9748154
    Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: August 29, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Boo Yang Jung, Jong Sik Paek, Choon Heung Lee, In Bae Park, Sang Won Kim, Sung Kyu Kim, Sang Gyu Lee
  • Patent number: 9675262
    Abstract: The disclosed technology generally relates to sensors comprising a two-dimensional electron gas (2DEG), and more particularly to an AlGaN/GaN 2DEG-based sensor for sensing signals associated with electrocardiograms, and methods of using the same. In one aspect, a sensor comprises a substrate and a GaN/AlGaN hetero-junction structure formed on the substrate and configured to form a two-dimensional electron gas (2DEG) channel within the GaN/AlGaN hetero-junction structure. The sensor additionally comprises Ohmic contacts connected to electrical metallizations and to the 2DEG channel, wherein the GaN/AlGaN hetero-junction structure has a recess formed between the Ohmic contacts. The sensor further comprises a dielectric layer formed on a top surface of the sensor.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 13, 2017
    Assignee: Stichting IMEC Nederland
    Inventors: Roman Vitushinsky, Peter Offermans
  • Patent number: 9633979
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 25, 2017
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 9425373
    Abstract: A light emitting module includes: a first substrate including a resin having insulation properties, and a copper component embedded in the resin; a second substrate placed above the copper component of the first substrate, and soldered to the copper component; a mounting electrode formed above the second substrate; and an LED placed above the second substrate, and gold-tin soldered to the mounting electrode.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takanori Aketa, Yoshiharu Sanagawa, Mitsuhiko Ueda, Takaaki Yoshihara, Shintaro Hayashi, Toshihiko Sato
  • Patent number: 9397019
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 19, 2016
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Patent number: 9313897
    Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Franz-Peter Kalz
  • Patent number: 9252125
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 2, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
  • Patent number: 9214454
    Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 15, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Liang Wang
  • Patent number: 9181081
    Abstract: According to one embodiment, an electrical component comprises a substrate, a functional element formed on the substrate, a first layer which includes through holes, and forms a cavity that stores the functional element on the substrate, and a second layer which is formed on the first layer, and closes the through holes. The first layer includes a first film, a second film on the first film, and a third film on the second film. A Young's modulus of the second film is higher than a Young's modulus of the first film and the third film.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 10, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kei Obara, Yoshiaki Sugizaki, Yoshiaki Shimooka
  • Patent number: 9165794
    Abstract: A electronic device includes: a circuit board; a semiconductor device, disposed on the circuit board; a cover material, disposed above the semiconductor device; a plurality of bonding wires, respectively connected between a plurality of first contact pads of the semiconductor device and a plurality of second contact pads of the circuit board; a first encapsulant, formed by a first material, arranged to encapsulate a plurality of second bonds formed by electrically connecting the bonding wires to the second contact pads; and a second encapsulant, formed by a second material that is different from the first material, arranged to encapsulate a plurality of first bonds formed by electrically connecting the bonding wires to the first contact pads.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: October 20, 2015
    Assignee: Himax Display, Inc.
    Inventor: Jia-Lung Tsai
  • Patent number: 9136399
    Abstract: A semiconductor device package is assembled using a jig that alters the shape of gel material disposed in a cavity in the package. In one embodiment, a jig having a concave bottom surface is inserted onto uncured gel material disposed within a cavity in a housing of the package to change a top surface of the gel from having a concave shape to a convex shape. The gel is then cured with the jig in place. When the jig is subsequently removed, the cured gel retains the convex shape, which helps to avoid any bond wires from being exposed. The re-shaped gel material reduces internal stresses during thermal cycling and can therefore reduce permanent damage to the package otherwise resulting from such thermal cycling.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stanley Job Doraisamy, Soon Kang Chan, Soo Choong Chee
  • Patent number: 9041211
    Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 26, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kenta Uchiyama
  • Patent number: 9034696
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 9023691
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 8994063
    Abstract: An organic light emitting diode display includes a flexible substrate, an organic light emitting diode disposed over the flexible substrate, and an encapsulation film disposed over the flexible substrate to encapsulate the organic light emitting diode, with the organic light emitting diode interposed between the encapsulation film and the flexible substrate. A thermal conduction layer contacts the flexible substrate, wherein the thermal conduction layer faces the organic light emitting diode and the flexible substrate is interposed between the thermal conduction layer and the organic light emitting diode. A first film is disposed over the encapsulation film, and a second film is disposed over the thermal conduction layer.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Seob Lee, Dong-Un Jin
  • Publication number: 20150068600
    Abstract: A chemical vapor deposited film includes silicon atoms, oxygen atoms, carbon atoms, and hydrogen atoms. The chemical vapor deposited film is formed by a plasma CVD method such that the concentration of the oxygen atoms is 10-35% by element.
    Type: Application
    Filed: January 16, 2013
    Publication date: March 12, 2015
    Inventors: Takayoshi Fujimoto, Masamichi Yamashita
  • Patent number: 8962395
    Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 24, 2015
    Assignee: ChipMOS Technologies Inc.
    Inventor: Geng-Shin Shen
  • Patent number: 8963309
    Abstract: A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 8962392
    Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Jing-Cheng Lin, Jui-Pin Hung, Szu Wei Lu
  • Patent number: 8963345
    Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 24, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Stephane Cros, Nicole Alberola, Jean-Paul Garandet, Arnaud Morlier
  • Patent number: 8946743
    Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 3, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Bong Kul Min
  • Patent number: 8941218
    Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nathan Perkins, Jonathan Abrokwah, Ricky Snyder, Scott A. Rumery, Robert G. Long
  • Patent number: 8937394
    Abstract: An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 20, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Ting Chen, Li-Wen Lai, Kun-Wei Lin, Teng-Yen Wang
  • Publication number: 20150014866
    Abstract: A method for producing a glass-like layer (3) on a substrate, e.g. a power semiconductor substrate (1), is disclosed. The method comprises the deposition of a glass-like layer vapor-deposited material with plasma-assisted electron beam evaporation. An electronic component can be produced using this method.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Simon Maus, Ulli Hansen
  • Patent number: 8933470
    Abstract: A display apparatus and a method of manufacturing the same includes a substrate including a plurality of organic layers and a plurality of inorganic layers, a display unit formed on the substrate and an encapsulation unit formed on the display, wherein the plurality of organic layers and the plurality of inorganic layers comprise at least a first organic layer, a first inorganic layer, a second organic layer, and a second inorganic layer which are sequentially stacked, and wherein an interfacial adhesion strength of the second organic layer is higher than an interfacial adhesion strength of the first organic layer.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Seon-Hee Kim
  • Patent number: 8922030
    Abstract: A semiconductor module is provided which is well protected against corrosion and/or other damage which can be caused by moisture and/or other harmful substances surrounding the semiconductor module. A method for producing such a semiconductor module is also provided.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8907225
    Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 9, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Nishkamraj U Deshpande, H. Fred Barsun, Ron Shoultz
  • Patent number: 8900928
    Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 2, 2014
    Assignee: Spansion LLC
    Inventors: Koji Taya, Masanori Onodera
  • Patent number: 8896019
    Abstract: A thin-film encapsulation for an optoelectronic semiconductor body includes a PVD layer deposited by a PVD method, and a CVD layer deposited by a CVD method, wherein the CVD layer is applied directly on the PVD layer, and the CVD layer is etched back such that the CVD layer only fills weak points in the PVD layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: November 25, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Franz Eberhard, Sebastian Taeger, Korbinian Perzlmaier
  • Patent number: 8847406
    Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: September 30, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Haruki Ito
  • Patent number: 8847415
    Abstract: Thermosetting resin compositions useful for liquid compression molding encapsulation of a silicon wafer are provided. The so-encapsulated silicon wafers offer improved resistance to warpage, compared to unencapsulated wafers or wafers encapsulated with known encapsulation materials.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Henkel IP & Holding GmbH
    Inventors: Jie Bai, Afranio Torres-Filho, Kathryn Bearden
  • Publication number: 20140264960
    Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: CREE, INC.
    Inventor: Cree, Inc.
  • Patent number: 8829686
    Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Sun Hong, Young-Min Kim, Jung-Woo Kim, Min-Ok Na, Hyo-Chang Ryu, Jong-Bo Shim
  • Patent number: 8815650
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 26, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventor: Reza Argenty Pagaila
  • Patent number: 8810047
    Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: August 19, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Publication number: 20140210112
    Abstract: An encapsulation structure for an optoelectronic component may include: a barrier thin-film layer for protecting an optoelectronic component against chemical impurities; a cover layer applied above the barrier thin-film layer and serving for protecting the barrier thin-film layer against mechanical damage; and an intermediate layer applied on the barrier thin-film layer between barrier thin-film layer and cover layer and including a curable material designed such that when the non-cured intermediate layer is applied to the barrier thin-film layer, particle impurities at the surface of the barrier thin-film layer are enclosed by the intermediate layer and the applied intermediate layer has a substantially planar surface, and that after the intermediate layer has been cured, mechanical loads on the barrier thin-film layer as a result of particle impurities during the application of the cover layer are reduced by the intermediate layer.
    Type: Application
    Filed: July 5, 2012
    Publication date: July 31, 2014
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Thilo Reusch
  • Patent number: 8791583
    Abstract: Mold pieces (105 and 110) for molding a layer of mold compound on the interconnect side of a bumped semiconductor wafer (118) include a primary cavity (117) and secondary cavities (120) into which excess mold compound from the primary cavity (117) flows. The secondary cavities (120) include a plunger (130) that asserts a predetermined backpressure that is equal to a desired mold compound pressure on the mold compound during molding. As most of the excess mold compound in the primary cavity (117) is forced to flow into the secondary cavities (120), this advantageously leaves a relatively thin layer of mold compound on the semiconductor wafer (118), which can then be removed, for example by grinding in a relatively short time. Mold piece (105) further comprises a movable cavity bar (115) that can be moved away from mold piece (105) after molding and be cooled to detach the molded substrate that adheres to the cavity bar.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: July 29, 2014
    Assignee: Advanced Systems Automation Ltd.
    Inventors: Hwee Seng Jimmy Chew, Dingwei Xia
  • Patent number: 8786111
    Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Joachim Mahler, Khalil Hosseini, Hans-Joerg Timme
  • Patent number: 8786102
    Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 22, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8779606
    Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choongbin Yim, Hae-Jung Yu, Taesung Park
  • Patent number: 8779567
    Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: July 15, 2014
    Assignee: Nichia Corporation
    Inventors: Takuya Noichi, Yuichi Okada
  • Patent number: 8779607
    Abstract: A method of manufacturing a device includes forming a covering layer having affinity for a filler to be injected into a space between a first base and a second base, on at least one of the opposing surfaces of the first base and the second base, and then injecting the filler into the space between the first base and the second base.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 15, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Hiroyuki Ode