Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A thin-film encapsulation for an optoelectronic semiconductor body includes a PVD layer deposited by a PVD method, and a CVD layer deposited by a CVD method, wherein the CVD layer is applied directly on the PVD layer, and the CVD layer is etched back such that the CVD layer only fills weak points in the PVD layer.

Abstract: Thermosetting resin compositions useful for liquid compression molding encapsulation of a silicon wafer are provided. The so-encapsulated silicon wafers offer improved resistance to warpage, compared to unencapsulated wafers or wafers encapsulated with known encapsulation materials.

Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side.

Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.

Abstract: An encapsulation structure for an optoelectronic component may include: a barrier thin-film layer for protecting an optoelectronic component against chemical impurities; a cover layer applied above the barrier thin-film layer and serving for protecting the barrier thin-film layer against mechanical damage; and an intermediate layer applied on the barrier thin-film layer between barrier thin-film layer and cover layer and including a curable material designed such that when the non-cured intermediate layer is applied to the barrier thin-film layer, particle impurities at the surface of the barrier thin-film layer are enclosed by the intermediate layer and the applied intermediate layer has a substantially planar surface, and that after the intermediate layer has been cured, mechanical loads on the barrier thin-film layer as a result of particle impurities during the application of the cover layer are reduced by the intermediate layer.

Abstract: Mold pieces (105 and 110) for molding a layer of mold compound on the interconnect side of a bumped semiconductor wafer (118) include a primary cavity (117) and secondary cavities (120) into which excess mold compound from the primary cavity (117) flows. The secondary cavities (120) include a plunger (130) that asserts a predetermined backpressure that is equal to a desired mold compound pressure on the mold compound during molding. As most of the excess mold compound in the primary cavity (117) is forced to flow into the secondary cavities (120), this advantageously leaves a relatively thin layer of mold compound on the semiconductor wafer (118), which can then be removed, for example by grinding in a relatively short time. Mold piece (105) further comprises a movable cavity bar (115) that can be moved away from mold piece (105) after molding and be cooled to detach the molded substrate that adheres to the cavity bar.

Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.

Abstract: A method of manufacturing a device includes forming a covering layer having affinity for a filler to be injected into a space between a first base and a second base, on at least one of the opposing surfaces of the first base and the second base, and then injecting the filler into the space between the first base and the second base.

Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract: An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes an organic light emitting element formed over a substrate and an encapsulation portion covering the organic light emitting element. Further, the encapsulation portion may include at least one organic layer and at least one inorganic layer, wherein ends of the inorganic layer and the organic layer directly contact the substrate, and wherein the organic layer is thicker than the inorganic layer.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract: A fiber-containing resin substrate for collectively encapsulating a semiconductor-device-mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor-device-forming surface of a wafer on which a semiconductor device is formed, including a resin-impregnated fibrous base material which is obtained by impregnating a fibrous base material with a thermosetting resin and semi-curing or curing the thermosetting resin and has a linear expansion coefficient (ppm/° C.) in an X-Y direction of less than 3 ppm, and an uncured resin layer formed of an uncured thermosetting resin on one side of the resin-impregnated fibrous base material.

Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.

Abstract: A device that includes a component and an encapsulation arrangement for the encapsulation of the component with respect to moisture and/or oxygen, wherein the encapsulation arrangement has a first layer and thereabove a second layer on at least one surface of the component, the first layer and the second layer each comprise an inorganic material, and the second layer is arranged directly on the first layer.

Abstract: An organic light emitting diode (OLED) display a includes: a substrate; an organic light emitting element on the substrate and including a first electrode, a light emission layer, and a second electrode; and an encapsulation layer on the substrate while covering the organic light emitting element. The encapsulation layer includes an organic layer and an inorganic layer. A mixed area, where organic materials forming the organic layer and inorganic materials forming the inorganic layer co-exist along a plane direction of the encapsulation layer, is formed at the boundary between the organic layer and the inorganic layer.

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.

Abstract: A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.

Abstract: The present invention provides a stacked organic light emitting device, comprising a first conductive layer, at least one intermediate conductive layer and a second conductive layer, and light emitting units disposed between the conductive layers, wherein at least two non-neighboring conductive layers among the conductive layers are conductive layers belonging to Group 1 such that they are electrically connected with each other to a common potential; at least one non-neighboring conductive layer among the conductive layers which are not electrically connected with the conductive layers belonging to Group 1 to a common potential are conductive layers belonging to Group 2 such that they are electrically connected with each other to a common potential; and the conductive layers belonging to Group 1 and the conductive layers belonging to Group 2 are connected with each other via a voltage regulator for alternately applying a positive voltage and a negative voltage.

Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

Abstract: A sealing film forming method is capable of forming a sealing film having high moisture permeability resistance in a shorter time and at lower cost. The sealing film forming method for forming a sealing film 13 that seals an EL device 12 includes forming a first inorganic layer 13a on a surface of the EL device 12; forming a hydrocarbon layer 13c on the first inorganic layer 13a; flattening the hydrocarbon layer 13c by softening or melting the hydrocarbon layer 13c; curing the hydrocarbon layer 13c; and forming a second inorganic layer 13e thicker than the first inorganic layer 13a on the hydrocarbon layer 13c after curing the hydrocarbon layer 13c.

Abstract: A semiconductor package includes a first semiconductor chip mounted to a substrate, a first encapsulant covering the first semiconductor chip and have first to fourth sidewall surfaces, and a chip stack mounted to the substrate and disposed on the first encapsulant. The chip stack includes a plurality of second semiconductor chips. A second encapsulant covers the chip stack. The second encapsulant may cover the first sidewall surface of the first encapsulant and expose the third sidewall surface of the first encapsulant.

Abstract: An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically.

Abstract: A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part.

Abstract: A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

Abstract: A semiconductor device includes: a case with an opening formed thereat; a semiconductor element housed inside the case; a first conductor plate housed inside the case and positioned at one surface side of the semiconductor element; a second conductor plate housed inside the case and positioned at another surface side of the semiconductor element; a positive bus bar electrically connected to the first conductor plate, through which DC power is supplied; a negative bus bar electrically connected to the second conductor plate, through which DC power is supplied; a first resin member that closes off the opening at the case; and a second resin member that seals the semiconductor element, the first conductor plate and the second conductor plate and is constituted of a material other than a material constituting the first resin member.

Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.

Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

Abstract: In a circuit device of the present invention, the lower surface side of a circuit board and part of side surfaces thereof are covered with a second resin encapsulant, and the upper surface side and the like of the circuit board are covered with a first resin encapsulant. Since heat dissipation to the outside of the circuit device is achieved mainly through the second resin encapsulant, a particle size of filler contained in the second resin encapsulant is made larger than a particle size of filler contained in the first resin encapsulant. Heat dissipation to the outside of the circuit device is greatly improved.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: A semiconductor device includes: a substrate including an electrode pad on a surface; a semiconductor chip placed on the substrate so as to be electrically connected to the electrode pad; a first resin layer which is formed on the substrate and is also filled between the substrate and the semiconductor chip; and a second resin layer, laminated on the first resin layer, which has an elastic modulus larger than that of the first resin layer.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.

Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.