Including Polysiloxane (e.g., Silicone Resin) Patents (Class 257/791)
-
Patent number: 6972495Abstract: An assembly including a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface; and conductive elastomeric posts formed by curing a conductive elastomeric material, wherein each of the contacts of the first microelectronic element is respectively aligned with one of the contacts of the second microelectronic element, and further wherein at least some of the contacts of the first element are connected to the respectively aligned contacts of the second element by the conductive elastomeric material.Type: GrantFiled: August 19, 2003Date of Patent: December 6, 2005Assignee: Tessera, Inc.Inventor: Joseph Fjelstad
-
Patent number: 6962957Abstract: An epoxy resin composition for semiconductor encapsulation comprising (A) an epoxy resin, (B) a phenolic resin, and (C) butadiene rubber particles having an average particle size of secondary particles of 100 ?m or smaller and having such a size distribution that the proportion of secondary particles having a particle size of 250 ?m or smaller is 97% by weight or more, and the proportion of secondary particles having a particle size of 150 ?m or smaller is 80% by weight or more. Component (C) is uniformly dispersed in the composition without forming coarse agglomerates to secure low stress properties.Type: GrantFiled: April 24, 2003Date of Patent: November 8, 2005Assignee: Nitto Denko CorporationInventors: Hideyuki Usui, Satoshi Okuda, Minoru Nakao
-
Patent number: 6946730Abstract: A semiconductor device includes a semiconductor chip generating heat, a pair of heat sinks, which face each other, to conduct heat from both surfaces of the chip, a pair of compressible insulating sheets, and a mold resin covering the chip, the heat sinks, and the sheets such that the sheets are exposed from the surface of the resin. The mold resin is prevented from covering the outer surfaces of the heat sinks, which are pressed by mold parts, and breakage of the chip is avoided during molding. The plates are insulated by the sheets, so no dedicated insulating sheets for the heat sinks are needed after the device is completed.Type: GrantFiled: February 27, 2004Date of Patent: September 20, 2005Assignee: Denso CorporationInventor: Takanori Teshima
-
Patent number: 6940177Abstract: A semiconductor package comprising a semiconductor wafer having an active surface comprising at least one integrated circuit, wherein each integrated circuit has a plurality of bond pads; and at least one cured silicone member covering at least a portion of the active surface, wherein at least a portion of each bond pad is not covered by the silicone member, the silicone member has a coefficient of linear thermal expansion of from 60 to 280 ?m/m° C. between ?40 and 150° C. and a modulus of from 1 to 300 MPa at 25° C., and the silicone member is prepared by the method of the invention.Type: GrantFiled: May 16, 2002Date of Patent: September 6, 2005Assignee: Dow Corning CorporationInventors: Stanton James Dent, Lyndon James Larson, Robert Thomas Nelson, Debra Charilla Rash
-
Patent number: 6916889Abstract: Epoxy resin compositions are disclosed which comprise (A) at least one silicone epoxy resin, (B) at least one hydroxyl-containing compound, (C) at least one anhydride curing agent, (D) at least one ancillary curing catalyst, and optionally at least one of thermal stabilizers, UV stabilizers, cure modifiers, coupling agents, or refractive index modifiers. Also disclosed are packaged solid state devices comprising a package, a chip (4), and an encapsulant (11) comprising an epoxy resin composition of the invention. A method of encapsulating a solid state device is also provided.Type: GrantFiled: May 1, 2003Date of Patent: July 12, 2005Assignee: General Electric CompanyInventors: Malgorzata Iwona Rubinsztajn, Slawomir Rubinsztajn
-
Patent number: 6913947Abstract: A multi-layer circuit board is manufactured by laminating and bonding together a plurality of resin films, on each of which a circuit pattern is directly drawn by injecting ink. The ink includes metal particles, having a diameter in the order of nanometers, dispersed therein. At the same time when the laminated resin films are bonded together under pressure and heat, the metal particles in the ink are sintered, thereby forming a solid electrical circuit printed on the resin film. Since the circuit pattern is directly drawn on the resin film, the process of manufacturing the multi-layer circuit board is simplified.Type: GrantFiled: October 8, 2003Date of Patent: July 5, 2005Assignee: Denso CorporationInventor: Masashi Totokawa
-
Patent number: 6867506Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.Type: GrantFiled: August 2, 2001Date of Patent: March 15, 2005Assignee: Intel CorporationInventor: Joseph C. Barrett
-
Patent number: 6861683Abstract: In an optoelectronic component assembly and a method for the production thereof, the optoelectronic component assembly includes an optoelectronic component arranged on a support element, which is surrounded by a closed dam. An encapsulation is arranged in an inner area of the dam, which encapsulates the optoelectronic component and includes two sealing materials. The inner area of the dam may be filled with a first sealing material up to the top edge of the optoelectronic component. The inner area of the dam located above the optoelectronic component is filled with a second transparent sealing material at least in one area of the window.Type: GrantFiled: March 30, 2002Date of Patent: March 1, 2005Assignee: Dr. Johannes Heidenhain GmbHInventors: Lutz Rissing, Florian Obermayer, Florian Schroll
-
Patent number: 6844568Abstract: There is disclosed a photoelectric conversion device which is manufactured by depositing numerous crystalline semiconductor particles of one conductivity type on a substrate having an electrode of one side to join the crystalline semiconductor particles to the substrate, interposing an insulator among the crystalline semiconductor particles, forming a semiconductor layer of the opposite conductivity type over the crystalline semiconductor particles, and connecting an electrode to the semiconductor layer of the opposite conductivity type, in which the insulator comprises a mixture or reaction product of polysiloxane and polycarbosilane. The insulator interposed among the crystalline semiconductor particles is free from defects such as cracking and peeling, so that a low cost photoelectric conversion device with high reliability can be provided.Type: GrantFiled: April 25, 2003Date of Patent: January 18, 2005Assignee: Kyocera CorporationInventors: Yoji Seki, Takeshi Kyoda, Yoshio Miura, Hisao Arimune
-
Patent number: 6831306Abstract: An extended length light emitting diode suitable for auto-insertion including an extended LED body region serving as a standoff or spacer to provide supported spacing from a circuit board to extend the LED die through a faceplate for suitable viewing and to serve as a structure through and about which the lower body portion of the LED and the LED leads can be stabilized and sealed to a printed circuit board. An alternative embodiment includes structure for sealing an LED to a faceplate.Type: GrantFiled: March 6, 2003Date of Patent: December 14, 2004Assignee: Daktronics, Inc.Inventor: Randy S. Uehran
-
Patent number: 6783692Abstract: A heat softening thermally conductive composition comprises: a matrix comprising a silicone resin, and a thermally conductive filler. The composition can be used as a thermal interface material in electronic devices. The composition is formulated to have any desired softening temperature.Type: GrantFiled: October 17, 2002Date of Patent: August 31, 2004Assignee: Dow Corning CorporationInventor: Dorab Edul Bhagwagar
-
Patent number: 6784555Abstract: Die attach adhesives and methods for their use, along with the devices that are obtained by the use of the methods. Using semiconductor chips as an example, the adhesives and the method for using them provides an interface between a chip (die) and the chip support. The method includes creating a space between the chip and the chip support of a given sized opening by using inorganic insulator particles having an average particle size of 1 &mgr;m to 1000 &mgr;m and a major axis to minor axis ratio of about 1.0 to 1.5.Type: GrantFiled: September 17, 2001Date of Patent: August 31, 2004Assignee: Dow Corning CorporationInventor: Michael John Watson
-
Patent number: 6784512Abstract: A photodiode having a resin film painted upon an opening through which signal light goes in and a dielectric multilayered film piled upon the resin film for reflecting noise light. The elasticity of the resin film prevents the dielectric multilayered film from transforming or exfoliating by alleviating inner stress due to piling of tens to hundreds of different rigid dielectric layers.Type: GrantFiled: March 20, 2002Date of Patent: August 31, 2004Assignee: Sumitomo Electric Industries, Ltd.Inventors: Akira Yamaguchi, Yoshiki Kuhara, Takashi Sasaki
-
Publication number: 20040155365Abstract: The preferred embodiments provide a lead frame wherein a first air vent 29 and a second air vent 30 are formed in an air vent forming region 32. When resin-molding, one end of this first air vent 29 is disposed within the cavity, whereby air in the cavity when resin-molding can be completely released to the outside of the cavity. As a result, a package after resin-molding includes no unfilled regions or voids, whereby a semiconductor device with excellent product quality can be provided. In the background, air in cavities could not be completely released when resin-molding since, for instance, one air vent was provided at a position apart from the cavity region, and unfilled regions or voids were created.Type: ApplicationFiled: February 6, 2004Publication date: August 12, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Isao Ochiai, Kazumi Onda
-
Patent number: 6774405Abstract: A light-emitting element is mounted in a cup-like portion formed on a substrate and a case. The cup-like portion is filled with a sealing member made of a light-transmissible resin. A layer made of a material having a refractive index lower than that of the sealing member is provided between the sealing member and a surface of the case.Type: GrantFiled: March 5, 2002Date of Patent: August 10, 2004Assignees: Toyoda Gosei Co., Ltd., Sanken Electric Co., Ltd.Inventors: Takemasa Yasukawa, Hideki Omoya, Satoshi Honda, Koji Tsukagoshi, Tsutomu Yokota
-
Publication number: 20040135269Abstract: A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the insulating layer over the fist conductive layer. Each of the first and second conductive layers is formed by discharging drops of a solvent containing fine particles of a conductive material. The insulating layer is formed by discharging drops of a solvent containing fine particles of an insulating material.Type: ApplicationFiled: July 23, 2003Publication date: July 15, 2004Applicant: Seiko Epson CorporationInventor: Tetsuya Otsuki
-
Patent number: 6762511Abstract: A device allows for continuous regulation of the composition of a fluid mixture that includes at least two components of different polarities. The device is designed, for example, to be inserted in a separation system that the device supplies with a carrier fluid of stabilized composition. The device includes a storage tank (3) receiving a mixture coming from the separation system and at least one auxiliary vessel (6) containing one of the components of the mixture. To control the transfer of this component from auxiliary vessel (6) to storage tank (3), the device further includes at least one tubular capacitive sonde (CS) totally immersed in the fluid mixture, a sonde (TS) for measuring the temperature of the mixture, and a sondc (LS) for measuring the mixture level in storage tank (3).Type: GrantFiled: March 19, 2001Date of Patent: July 13, 2004Assignee: Hitachi, Ltd.Inventors: Yuichi Satsu, Harukazu Nakai, Akio Takahashi, Masao Suzuki, Katsuo Sugawara
-
Patent number: 6762510Abstract: A flexible monolithic integrated circuit which is essentially formed from flexible circuit elements, connecting elements between the flexible circuit elements, and a flexible coating which comprises at least one layer of a coating material comprising a polymer, is suitable as a small and convenient integrated circuit for electronic devices on flexible data carriers for the logistic tracking of objects and persons. The invention also relates to a method of manufacturing a flexible integrated monolithic circuit whereby integrated monolithic circuit elements and connecting elements are formed in and on a semiconductor substrate, the main surface of the integrated circuit elements facing away from the semiconductor substrate are coated with a polymer resin, and the semiconductor substrate is removed. The method is based on conventional process steps in semiconductor technology and leads to a flexible integrated monolithic circuit in a small number of process steps.Type: GrantFiled: May 8, 2002Date of Patent: July 13, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Johann-Heinrich Fock, Wolfgang Schnitt, Hauke Pohlmann, Andreas Gakis, Michael Burnus, Martin Schaefer, Henricus Godefridus Rafael Maas, Theodorus Martinus Michielsen, Ronald Dekker
-
Publication number: 20040124547Abstract: A semiconductor device includes at least one semiconductor structure having a plurality of external connection portions on an upper surface, and an insulating member which is made of a resin containing reinforcing materials and arranged on a side of the semiconductor structure. An insulating film is formed on the upper surface of the semiconductor structure, except the external connection portions, and on an upper surface of the insulating member. A plurality of upper wirings each of which has a connection pad portion are located on an upper side of the insulating film and electrically connected to a corresponding one of the external connection portions of the semiconductor structure. The connection pad portion of at least one of the upper wirings is arranged above an upper surface of the insulating member.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Applicant: Casio Computer Co., Ltd.Inventor: Hiroyasu Jobetto
-
Patent number: 6733902Abstract: A liquid epoxy resin composition includes (A) a liquid epoxy resin, (B) a curing agent, (C) a curing accelerator, (D) an inorganic filler, and (E) a silicone-modified resin resulting from addition reaction of an alkenyl-containing epoxy or phenolic resin with an organopolysiloxane, the liquid epoxy resin composition curing into a product having a Tg of 30-120° C. and a specific dynamic viscoelasticity behavior. The composition is adherent to silicon chips, the cured product is highly resistant to heat and thermal shocks, and the composition is useful as sealant for flip chip type semiconductor devices.Type: GrantFiled: August 15, 2002Date of Patent: May 11, 2004Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Kazuaki Sumita, Tatsuya Kanamaru, Toshio Shiobara
-
Publication number: 20040084784Abstract: A packaged electronic component and a method for packaging an electronic component are proposed, in which a chip is attached to the upper side of a die pad. The die pad and the chip are enclosed by a plastic molding compound. A gel is disposed on the upper side of the chip and on the lower side of the die pad.Type: ApplicationFiled: December 22, 2003Publication date: May 6, 2004Inventors: Stefan Mueller, Frieder Haag
-
Patent number: 6724079Abstract: A wire bond-less electronic component is for use with a circuit external to the wire bond-less electronic component. The wire bond-less electronic component includes a support substrate (110, 410), an electronic device (130) over the support substrate, and a cover (140, 440, 540) located over the electronic device and the support substrate. The cover includes an interconnect structure (141, 441, 541) electrically coupled to the electronic device and adapted to electrically couple together the electronic device and the circuit for providing impedance transformation of an electrical signal between the electronic device and the circuit.Type: GrantFiled: January 4, 2002Date of Patent: April 20, 2004Assignee: Motorola, Inc.Inventors: Lakshminarayan Viswanathan, Pierre-Marie Piel, Garry D. Funk, Robert Paul Davidson
-
Patent number: 6724093Abstract: Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device.Type: GrantFiled: July 24, 2001Date of Patent: April 20, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: John R. Cutter
-
Publication number: 20040061243Abstract: A window-type semiconductor package and a fabrication method thereof are provided. A substrate having an opening is mounted with at least a chip in a manner that, a conductive area of an active surface of the chip is exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. A non-conductive material is applied over the conductive area of the chip. An upper encapsulant is formed to encapsulate the chip, and a lower encapsulant is formed to encapsulate the bonding wires and the non-conductive material. The non-conductive material interposed between the chip and the lower encapsulant helps prevent the chip from cracking at end portions thereof due to shrinkage of the lower encapsulant, and also helps secure the bonding wires in position within the opening of the substrate without causing wire-sweeping, such that reliability and yield of the semiconductor package can be assured.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventor: Jin-Chuan Bai
-
Patent number: 6710377Abstract: A light emitting device includes a semiconductor light emitting element and a silicone resin provided to embed said semiconductor light emitting element, where silicone resin has a hardness not lower than 50 in JISA value. The use of a silicone resin as the resin for sealing the semiconductor light emitting elements instead of conventional epoxy resins can reduce the possibility of cracks, exfoliation, breakage of wire, etc. that were often caused by conventional epoxy resins, and can also improve the resistance to whether and light.Type: GrantFiled: April 9, 2002Date of Patent: March 23, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Kenji Shimomura
-
Publication number: 20040021234Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.Type: ApplicationFiled: June 30, 2003Publication date: February 5, 2004Inventor: Kazutaka Shibata
-
Patent number: 6663943Abstract: A surface acoustic wave device includes a SAW element that is mounted on a substrate. Grooves are provided in the substrate at the outer periphery of the SAW element, and a flexible resin layer is provided at the inner portion of the grooves so as to cover the SAW element. An outer resin layer that is harder than the flexible resin layer is provided at the exterior of the flexible resin layer. This configuration facilitates reduction in size and profile of the surface acoustic wave device, contributes to reduction in cost, and exhibits high environmental resistance.Type: GrantFiled: June 19, 2001Date of Patent: December 16, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Michio Kadota
-
Patent number: 6664648Abstract: A method and an apparatus are described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like consistency is coated substantially with full coverage onto a lower contact area of the integrated circuit. Whereupon the integrated circuit is joined together, by the compensating layer, with the carrier element after a relative alignment in order then to produce an electrical connection between the integrated circuit and conductor tracks of the carrier element via electrical lines surmounting the thickness of the compensating layer. Whereupon the compensating layer is cured resulting in an increased volume of the compensating layer.Type: GrantFiled: March 16, 2001Date of Patent: December 16, 2003Assignee: Infineon Technologies AGInventors: Johann Winderl, Christian Hauser, Martin Reiss
-
Patent number: 6661076Abstract: A semiconductor device in which the potential of a conductive support substrate can be kept to be a predetermined potential, while an SOI substrate is used as a chip substrate, without adding a new step and providing a rear electrode, is provided. In a chip, on the main surface of a first Si substrate of a P-type, a SiO2 film and a second Si substrate of a P-type are laminated in this order. The chip has, in the second Si substrate, isolation trenches, an outermost isolation trench, a plurality of element forming regions isolated by these trenches, second element forming regions, a peripheral region, and a peripheral region connection wiring which connects a contact region of the peripheral region with a contact region connected with a predetermined potential, for example, a ground potential in the second element forming region surrounded by, for example, the isolation trench.Type: GrantFiled: October 30, 2001Date of Patent: December 9, 2003Assignee: NEC Electronics CorporationInventors: Masahiro Toeda, Kazunari Takasugi
-
Patent number: 6655022Abstract: A method of implementing a micro BGA is introduced. More specifically, the method discloses packaging an integrated circuit into an integrated circuit assembly. The method first mounts polyimide tape to a lead frame. The polyimide tape serves as a substrate for the integrated circuit package. Next, a piece of elastomer is coupled to said polyimide tape. Then an integrated circuit die is attached to said elastomer. Lead beams are then bonded from bond pads on said die to said lead frame. Solder balls are attached to said lead frame. The attached solder balls may be located beyond the area of said die.Type: GrantFiled: September 24, 1998Date of Patent: December 2, 2003Assignee: Intel CorporationInventors: Steven R. Eskildsen, Richard B. Foehringer, Deborah S. Kaller
-
Patent number: 6653731Abstract: A top surface of a LSI chip having a structure of a bare chip is provided with bumps, and a protective resin is provided for at least side surfaces of the LSI chips. The LSI chip is prevented from being chipped off or cracked because of protective resin provided for the side surfaces of the LSI chip. The invention provides a semiconductor device and a method for fabricating the same, in which the chip or a package thereof is prevented from being damaged, and thereby yield rate of the semiconductor device can be heightened. Since the numbers of the parts of the semiconductor device and the steps of using jigs and tools necessary for the fabrication process are reduced, fabricating cost of the semiconductor device can be cut down.Type: GrantFiled: February 15, 2001Date of Patent: November 25, 2003Assignee: NEC CorporationInventors: Yoshimasa Kato, Masamoto Tago
-
Patent number: 6649258Abstract: A heat conductive silicone composition comprising (A) an alkenyl group-bearing organopolysiloxane, (B) an organohydrogenpolysiloxane having Si—H groups on side chains, (C) an organohydrogenpolysiloxane having an Si—H group at either end, (D) a filler consisting of aluminum powder and zinc oxide powder in a weight ratio of from 1/1 to 10/1, (E) a platinum catalyst, and (F) a regulator has a high thermal conductivity and maintains flexibility even when exposed to heat for an extended period of time.Type: GrantFiled: April 29, 2002Date of Patent: November 18, 2003Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Kunihiro Yamada, Kenichi Isobe
-
Patent number: 6645643Abstract: A polymeric composition for making semiconductor device packaging includes at least one epoxy resin, at least one curing agent in an amount between 30 and 110 parts by weight per 100 parts by weight of the epoxy resin, at least one silica-based reinforcing filler in an amount between 300 and 2300 parts by weight per 100 parts of the epoxy resin, and at least one control agent for a rheology of the polymeric composition. The at least one control agent may be substantially free from polar groups and present in an amount between 0.1 and 50 parts by weight per 100 parts by weight of the epoxy resin. The invention also relates to a plastic packaging material for microelectronic applications which may be obtained from the above polymeric composition, and to a semiconductor electronic device including such packaging material.Type: GrantFiled: April 27, 2001Date of Patent: November 11, 2003Assignees: STMicroelectronics S.r.l., Toshiba Chemical Kawaguchi WorksInventors: Roberto Zafarana, Antonino Scandurra, Salvatore Pignataro, Yuichi Tenya, Akira Yoshizumi
-
Patent number: 6621173Abstract: A semiconductor device having a semiconductor chip; a semiconductor chip attachment element facing the semiconductor chip, at least one interconnect on the surface of the semiconductor chip attachment element; and at least one member consisting of a metal or metal alloy that electrically connects the semiconductor chip with the interconnects; wherein the semiconductor chip is bonded to the semiconductor chip attachment element by an adhesive and at least a portion of at least one member that electrically connects the semiconductor chip with at least one interconnect is sealed or imbedded with a sealant/filling agent, and the complex modulus of at least one of the adhesive and the sealant/filling agent is not greater than 1×108 Pa at −65° C. and a shear frequency of 10 Hz.Type: GrantFiled: January 14, 2000Date of Patent: September 16, 2003Assignee: Dow Corning Toray Silicone Co., Ltd.Inventors: Kimio Yamakawa, Minoru Isshiki, Yoshiko Otani, Katsutoshi Mine
-
Publication number: 20030168749Abstract: A semiconductor device can perform resin sealing of an under-fill region and peripheral portion on the side of a semiconductor chip in the same process step, with shortening periods required for filling and curing the under-fill resin and avoiding formation of an internal void, and can simplify fabrication process and component parts. The semiconductor device includes a through opening provided at a predetermined position of the wired substrate, an under-fill region as a gap portion between the wired substrate and the semiconductor chip, and a molded resin portion as peripheral portion along side edge of the semiconductor chip.Type: ApplicationFiled: May 19, 2003Publication date: September 11, 2003Inventor: Masahiro Koike
-
Patent number: 6613449Abstract: A solventless non-filler underfill material for COF mounting comprising an organic material, which is used to fill the gap between an FPC having a polyimide film substrate and a copper circuit layer having a thickness of 9 &mgr;m or smaller and an IC chip mounted on the FPC, exhibits such adhesion as to destroy a silicon wafer in a polyimide film/silicon wafer adhesion test, and provides a cured film having a tensile modulus of 150 kg/mm2 or less.Type: GrantFiled: January 29, 2002Date of Patent: September 2, 2003Assignee: UBE Industries, Ltd.Inventors: Hiroaki Yamaguchi, Masafumi Kohda
-
Patent number: 6614123Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.Type: GrantFiled: July 31, 2001Date of Patent: September 2, 2003Assignee: ChipPAC, Inc.Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
-
Publication number: 20030155664Abstract: In a liquid epoxy resin composition comprising a liquid epoxy resin, a curing agent, a curing accelerator, and an inorganic filler, the liquid epoxy resin is a mixture of (a) a liquid epoxy resin containing two or less epoxy functional groups and (b) a solid epoxy resin containing two or more epoxy functional groups in a weight ratio (a)/(b) of from 9/1 to 1/4, having a viscosity of up to 10,000 poises at 25° C. as measured by an E type viscometer. The composition is adherent to silicon chips, the cured product is highly resistant to humidity and thermal shocks, and the composition is useful as sealant for semiconductor devices.Type: ApplicationFiled: December 24, 2002Publication date: August 21, 2003Inventors: Kazuaki Sumita, Haruyoshi Kuwabara, Toshio Shiobara
-
Patent number: 6593663Abstract: An electronic device includes two microchips and a bonding layer with which the microchips are bonded together. The bonding layer is a silicone-type adhesive film, which has a glass transition temperature higher than +120° C. or lower than −40° C. Therefore, the influence of the variation in the elastic modulus of the bonding layer due to the glass transition on the electronic characteristic of one of the microchips is substantially eliminated in the temperature range between −40° C. and +120° C. Moreover, the elastic modulus in the temperature range between −40° C. and +120° C. is lowered. Therefore, the influence of a thermal stress in the one of the microchips on the electronic characteristic is suppressed.Type: GrantFiled: July 3, 2002Date of Patent: July 15, 2003Assignee: Denso CorporationInventors: Toshiya Ikezawa, Masaaki Tanaka, Takashige Saitou
-
Patent number: 6586105Abstract: The invention provides a packaging structure applied to an automotive component having semiconductors and electronic parts mounted on a ceramic base, characterized in that the semiconductors and electronic parts are partly or entirely sealed with a thixotropic silicone gel which has a thixotropy index of about 1.5-3.6 and a penetration depth of about 6-10 mm and a rate of change in viscosity of less than 10% of the initial value.Type: GrantFiled: April 3, 2001Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Masahiko Asano, Mutsumi Watanabe, Kunito Nakatsuru, Hiroatsu Tokuda
-
Patent number: 6563196Abstract: The invention aims to easily suppress chipping on the reverse face of a semiconductor when a semiconductor wafer is cut, and to make it possible to easily prevent edge contact of bonding wires. A resin film (14) is formed at the periphery of boundary regions (corresponding to 6) provided for chip separation of semiconductor chips (8). Then, the semiconductor wafer (1) is diced by cutting along the central part (corresponding to 7) of the boundary region. Furthermore, in a semiconductor device having semiconductor elements formed on a semiconductor substrate, the resin film (14) is formed on a part of the boundary regions provided for chip separation, matching the bonding pads (3) of each chip. Alternatively, the resin film (14) is formed with a predetermined width on the periphery of the abovementioned boundary regions.Type: GrantFiled: July 26, 2001Date of Patent: May 13, 2003Assignee: NEC Electronics CorporationInventor: Yuichi Miyagawa
-
Patent number: 6555905Abstract: A heat conductive silicone composition comprising (A) an alkenyl group-bearing organopolysiloxane, (B) an organohydrogenpolysiloxane having at least two Si—H groups, (C) a filler consisting of aluminum powder and zinc oxide powder in a weight ratio of from 1/1 to 10/1, (D) an organosilane having a long-chain alkyl groups, (E) platinum or a platinum compound, and (F) a regulator has a high thermal conductivity and maintains flexibility even when exposed to heat for an extended period of time.Type: GrantFiled: June 25, 2001Date of Patent: April 29, 2003Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Kunihiro Yamada, Kazuhiro Toba, Takayuki Takahashi, Kenichi Isobe
-
Publication number: 20030071366Abstract: Epoxy resin compositions are disclosed which comprise (A) at least one silicone epoxy resin, (B) at least one hydroxyl-containing compound, (C) at least one anhydride curing agent, (D) at least one ancillary curing catalyst, and optionally at least one of thermal stabilizers, UV stabilizers, cure modifiers, coupling agents, or refractive index modifiers. Also disclosed are packaged solid state devices comprising a package, a chip (4), and an encapsulant (11) comprising an epoxy resin composition of the invention. A method of encapsulating a solid state device is also provided.Type: ApplicationFiled: August 21, 2001Publication date: April 17, 2003Applicant: General Electric CompanyInventors: Malgorzata Iwona Rubinsztajn, Slawomir Rubinsztajn
-
Patent number: 6545368Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a substrate and the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material. The oxidizable metal layer which adheres to the substrate is applied over a specific portion of the substrate. The oxidizable metal layer is oxidized to form a metal oxide layer which does not adhere to encapsulant materials.Type: GrantFiled: April 25, 2002Date of Patent: April 8, 2003Assignee: Micron Technology, Inc.Inventor: Richard W. Wensel
-
Patent number: 6541874Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.Type: GrantFiled: June 6, 2001Date of Patent: April 1, 2003Assignee: Tessera, Inc.Inventors: Tan Nguyen, Craig S. Mitchell, Thomas H. DiStefano
-
Patent number: 6518186Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein a residual organic compound layer on the surface of a substrate is used to facilitate removal of unwanted encapsulant material. An organic compound layer which inherently forms on the substrate during the fabrication of the substrate or during various chip attachment processes is masked in a predetermined location with a mask. The substrate is then cleaned to remove the organic compound layer. The mask protects the masked portion of the organic material layer which becomes a release layer to facilitate gate break. An encapsulant mold is placed over the substrate and chip and an encapsulant material is injected into the encapsulant mold cavity through an interconnection channel. The release layer is formed in a position to reside as the bottom of the interconnection channel. Preferably, the interconnection channel has a gate adjacent the encapsulant mold cavity.Type: GrantFiled: May 19, 2000Date of Patent: February 11, 2003Assignee: Micron Technology, Inc.Inventor: Richard W. Wensel
-
Publication number: 20030020149Abstract: A dielectric substrate for laser working contains a substance having a size of a half to 10 times of a laser light wavelength and different in refractive index from a material of the dielectric substrate. This substance enhances the absorption of a laser beam. Due to this, the energy loss in laser beam is transformed into the heat of fusion to form a penetration hole, thereby forming a well-formed penetration hole. The substance different in refractive index from the dielectric substrate material uses bubbles when the dielectric substrate is a quartz glass substrate, and a glass bead or fiber when it is a resin substrate.Type: ApplicationFiled: September 17, 2002Publication date: January 30, 2003Inventors: Hiroshi Ogura, Yoshikazu Yoshida
-
Patent number: 6507122Abstract: An integrated circuit chip package wherein the chip is encapsulated prior to mechanical bonding to a packaging substrate. The package provides a continuous adhesive interface between the encapsulated chip and surrounding encapsulant, and the substrate. This structure eliminates discontinuities in flatness and their associated stress states resulting in more reliable package contacts.Type: GrantFiled: July 16, 2001Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventor: Edmund D. Blackshear
-
Patent number: 6506869Abstract: A one-pack type epoxy resin composition is desclosed. The composition comprises a low-viscosity epoxy resin and an acid anhydride hardener, and has a viscosity of 250 P or less at 25° C. The hardener is an imide oligomer comprising an imide unit and having an acid anhydride group at the terminal thereof. The imide unit is represented by formula I: wherein A represents an asymmetric aromatic tetracarboxylic dianhydride residue or alicyclic tetracarboxylic dianhydride residue; and B represents a diaminopolysiloxane residue.Type: GrantFiled: September 25, 2001Date of Patent: January 14, 2003Assignee: Ube Industries, Ltd.Inventors: Hiroaki Yamaguchi, Masafumi Kohda
-
Publication number: 20020185752Abstract: The adhesion between a protective layer, which covers a wiring layer, and a potting material, which covers a microchip, in a hybrid IC is improved without placing an additional material between the protective layer and the potting material. The potting material is separated from other electronic devices on the hybrid IC. To improve adhesion, the surface roughness of the protective layer is increased by adding insulating particles to the protective layer, striking the surface of the protective layer with ceramic particles, or replicating a mesh pattern of a screen mask on the surface of the protective layer. To keep the potting material separated from the other electronic devices, another potting material for covering the electronic devices, which is more viscous than the potting material for covering the microchip, is potted and hardened before the potting material for covering the microchip is potted.Type: ApplicationFiled: May 15, 2002Publication date: December 12, 2002Inventors: Takeshi Ishikawa, Takashi Nagasaka