With Heat Sink Embedded In Encapsulant Patents (Class 257/796)
  • Patent number: 10497644
    Abstract: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 3, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hiroaki Matsubara, Yasumasa Kasuya
  • Patent number: 10431529
    Abstract: A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 1, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Shoji Yasunaga, Akihiro Koga
  • Patent number: 10396023
    Abstract: The semiconductor device includes a multi-layered substrate having an insulating plate and a circuit plate, a semiconductor chip having a front surface attached with a main electrode and a control electrode formed thereon, and a back surface fixed to the circuit plate, a first wiring substrate which includes a first conductive member and is placed so as to face the main electrode connected electrically to first conductive member, a second wiring substrate which includes a second conductive member, is placed so as to face the control electrode, and has an opening, and a conductive post having one end and another end, the one end being connected electrically and mechanically to the control electrode, and the other end being connected electrically and mechanically to the second conductive member. The first conductive member is thicker than the second conductive member, and the first wiring substrate is disposed within the opening.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuki Inaba, Daisuke Inoue, Shin Soyano
  • Patent number: 10396018
    Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Chan Lam Cha, Wei Han Koo, Andreas Kucher, Theng Chao Long
  • Patent number: 9978661
    Abstract: Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Oleg Feygenson, Sang Il Kim, Youngbae Kim, Jichul Kim, Seungkon Mok, Jungsu Ha
  • Patent number: 9953961
    Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Yokoyama, Masaaki Ochiai, Atsushi Maruyama, Tomonori Seki, Shinichiro Matsunaga
  • Patent number: 9870975
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hua Wang, Po-Yao Lin, Shu-Shen Yeh, Kuang-Chun Lee, Shin-Puu Jeng, Shyue-Ter Leu, Cheng-Lin Huang, Hsiu-Mei Yu
  • Patent number: 9837368
    Abstract: A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 5, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Peter R. Harper, Martin Mason, Arkadii V. Samoilov
  • Patent number: 9078347
    Abstract: An electronic component housing unit includes: a substrate including a mounting region on which an electronic component is mounted; a connection conductor extending from a top face to a bottom face of the substrate, the connection conductor being electrically connected to the electronic component; a wiring conductor disposed on the bottom face of the substrate, one end of the wiring conductor being electrically connected to the connection conductor, another end of the wiring conductor being drawn out from a side face of the substrate; and a ground conductor disposed on the bottom face of the substrate, the ground conductor forming a coplanar line along with the wiring conductor. A bottom face of the wiring conductor is located above a bottom face of the ground conductor.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: July 7, 2015
    Assignee: KYOCERA Corporation
    Inventor: Mahiro Tsujino
  • Patent number: 9054023
    Abstract: An integrated circuit (IC) package having a packaging substrate, an IC disposed onto the packaging substrate, and a rigid support member attached to the substrate layer through an adhesive spacer is provided. The packaging substrate includes multiple decoupling capacitors positioned thereon around the IC. A heat sink is placed over the IC. The rigid support member provides enhanced structural support for the IC packaging and there is ample space between a bottom surface of the rigid support member and the packaging substrate to allow the placement of the decoupling capacitors underneath the rigid support member.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 9, 2015
    Assignee: Altera Corporation
    Inventor: Teck-Gyu Kang
  • Patent number: 9048211
    Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 2, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9041197
    Abstract: A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. A stem is connected to the element securing member, and a cap is secured to the stem. The cap covers the semiconductor element and the element securing member. The stem and the element securing member are made of the same material.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 26, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takashi Motoda
  • Patent number: 9033515
    Abstract: A heat dissipation device of a light engine for a projector has a housing, a fan module, a light engine and a heat sink. The light engine is positioned in the housing and connected to the heat sink. The heat sink is positioned out of the housing. The housing has a fan-enclosed flow channel attached on an outer surface of the housing. The fan module is guided by the fan-enclosed flow channel to the heat sink to enhance heat dissipation efficiency of the light engine for the projector.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 19, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ming-Chih Sun, Kai Huang
  • Patent number: 9035329
    Abstract: The light-emitting device having an equivalent circuit, includes at least four terminals, numbered from first terminal to fourth terminal, for electrical power feeding; a first light-emitting diode, arranged between the first terminal and the second terminal, configured to not emit light when a voltage is applied between the second terminal and one of the third terminal and the fourth terminal, and configured to emit light when a. voltage is applied between the first terminal and one of the third terminal and the four the terminal; and a second light-emitting diode, arranged between the third terminal and the fourth terminal, and configured to not emit light when the voltage is applied between the third terminal and one of the first terminal and the second terminal and configured to emit light when a voltage is applied between the fourth terminal and one of the first terminal and the second terminal.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 19, 2015
    Assignee: Epistar Corporation
    Inventors: Chao-Hsing Chen, Chien-Kai Chung, Hui-chen Yeh, Yi-Wen Ku
  • Patent number: 9018751
    Abstract: A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David R Hembree, Alan G. Wood
  • Patent number: 9013035
    Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 9013031
    Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Jichul Kim, Kyol Park, Seongho Shin
  • Patent number: 9006870
    Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor Inc.
    Inventors: Xiaotian Zhang, Hua Pan, Ming-Chen Lu, Jun Lu, Hamza Yilmaz
  • Patent number: 8994167
    Abstract: A semiconductor device includes a plurality of semiconductor elements each having a front surface and a back surface; a front surface-side heatsink that is positioned on a front-surface side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a back surface-side heatsink that is positioned on a back surface-side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a sealing material that covers the semiconductor device except for a front surface of the front surface-side heatsink and a back surface of the back surface-side heatsink; a primer that is coated on at least one of the front surface-side heatsink and the back surface-side heatsink and improves contact with the sealing member; and a protruding portion positioned between the plurality of semiconductor elements, on at least one of the back surface of the front surface-side heatsink and the front surface of the back surface-side heatsink.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 31, 2015
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Takuya Kadoguchi, Shingo Iwasaki, Tomohiro Miyazaki, Masayoshi Nishihata, Tomomi Okumura
  • Patent number: 8971044
    Abstract: A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Keiji Okumura, Takukazu Otsuka, Masao Saito
  • Patent number: 8946871
    Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: February 3, 2015
    Assignee: LSI Corporation
    Inventors: Zeki Z. Celik, Allen S. Lim, Atila Mertol
  • Publication number: 20150014840
    Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, the encapsulating body including a top surface and a side surface, and a plurality of heat sink plates embedded in the encapsulating body, each of the heat sink plates including an upper portion and a lower portion, the upper portion having an upper surface exposed from the top surface of the encapsulating body, the lowering portion being embedded in the encapsulating body, each of the plurality of heat sink plates being spaced from the semiconductor chip by the encapsulating body. The lower portion of each of the plurality of the heat sink plates includes a protrusion extending horizontally to an outside of an outer edge of the lower portion.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Inventor: Yuji WATANABE
  • Patent number: 8912670
    Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Deepak Kulkarni, Chia-Pin Chiu, Tannaz Harirchian, John S. Guzek
  • Patent number: 8912640
    Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 16, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Keita Takada, Tadatoshi Danno, Hirokazu Kato
  • Patent number: 8890311
    Abstract: A power conversion device is provided with a plurality of semiconductor modules. Each semiconductor module includes a heat dissipation member, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is fixed to the heat dissipation member. The semiconductor element is mounted on the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end, and at least part of the heat dissipation member. The semiconductor modules each form a unit.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shinsuke Nishi, Shogo Mori
  • Patent number: 8872321
    Abstract: One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 8872330
    Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, Berthold Hahn
  • Patent number: 8841694
    Abstract: A LED module with separate heat-dissipation and electrical conduction paths is disclosed, having a metal substrate; a plastic layer, including one or more hollow regions, and attached to the metal substrate; one or more conducting elements attached to the plastic layer; one or more LED chips positioned in the one or more hollow regions of the plastic layer and directly attached to the metal substrate; and a plurality of conducting wires for electrically connecting the one or more conducting elements and the one or more LED chips; wherein inner sides of the one or more hollow regions include one or more inclined surfaces each having an included angle with an upper surface of the metal substrate, and the included angle is between 90˜180 degrees.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 23, 2014
    Assignee: LITUP Technology Co. Ltd.
    Inventors: Chih-Chen Lin, Tsung-I Lin, Ying-Che Sung
  • Patent number: 8779581
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: July 15, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Patent number: 8779570
    Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seong Bo Shim, TaeWoo Kang, Yong Hee Kang
  • Publication number: 20140167296
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a sacrificial microchannel material on a device, forming an overmold material on the sacrificial microchannel material, and vaporizing the sacrificial microchannel material to form microchannel structures in the overmold that are conformal to the surfaces of the device.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: INTEL CORPORATION
    Inventor: Arnab Choudhury
  • Patent number: 8754521
    Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Leo M. Higgins, III, Yuan Yuan
  • Patent number: 8749051
    Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 10, 2014
    Assignee: ABB Research Ltd
    Inventors: Slavo Kicin, Nicola Schulz, Munaf Rahimo, Raffael Schnell
  • Patent number: 8703539
    Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsiun Lee, Kai-Chiang Wu
  • Patent number: 8686545
    Abstract: A semiconductor device according to the present disclosure includes: a plate (13) having a through hole (15); a metal column (16) fixed to the through hole with an insulating member (17) interposed therebetween, and having a projection projecting from the upper surface of the plate; a semiconductor element (12) fixed to the projection; a lead frame (11) electrically connected to the semiconductor element; and a package (14) covering the semiconductor element, and also covering at least part of each of the plate, the metal column, and the lead frame. The lower surface (13b) of the plate is exposed from the package.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Tatsuo Sasaoka
  • Patent number: 8669140
    Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kesvakumar V. C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan
  • Patent number: 8659146
    Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: February 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Bauer, Anton Kolbeck
  • Patent number: 8653673
    Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 18, 2014
    Assignee: Raytheon Company
    Inventors: Robert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
  • Patent number: 8633060
    Abstract: A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Patent number: 8624366
    Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 7, 2014
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Yu-Shan Hu
  • Patent number: 8618674
    Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 8598616
    Abstract: Disclosed are a light emitting device and a light unit using the same. The light emitting device includes a body, a light emitting diode installed in the body, a plurality of lead frames disposed in the body and electrically connected to the light emitting diode; and a heat dissipation member received in the body, thermally connected to the light emitting diode, and having a plurality of heat dissipation fins exposed from a lower surface of the body.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 3, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Gun Kyo Lee
  • Patent number: 8592851
    Abstract: A surface mount optical semiconductor device and circuit can efficiently transfer and dissipate heat even when being mounted together with electronic circuit components. The optical semiconductor device can include a lead frame having a concave portion for mounting a light-emitting element therein and a pair of electrode terminals connected to a board. A sealing resin portion can be provided for sealing a surrounding region of the concave portion. A bottom surface of the concave portion is located at a predetermined distance from a connecting surface on which the pair of electrode terminals is connected to the board. The bottom surface of the concave portion can also be exposed from a bottom surface of the sealing resin portion. Thus, the bottom surface of the concave portion and the device in general can be air-cooled efficiently.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: November 26, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Hiroyuki Takayama
  • Publication number: 20130300004
    Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: DaeSik Choi, JoungIn Yang, Sang Mi Park, WonIl Kwon, YiSu Park
  • Patent number: 8581374
    Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 12, 2013
    Assignee: Marvell International Ltd.
    Inventors: Chender Chen, Chenglin Liu, Shiann-Ming Liou
  • Patent number: 8581387
    Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8575769
    Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: November 5, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Publication number: 20130270721
    Abstract: An apparatus has external and/or internal capacitive thermal material for enhanced thermal package management. The apparatus includes an integrated circuit (IC) package having a heat generating device. The apparatus also includes a heat spreader having a first side that is attached to the IC package. The apparatus also includes capacitive thermal material reservoirs contacting the first side of the heat spreader. The capacitive thermal material reservoirs may be disposed laterally relative to the heat generating device.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Victor A. Chiriac, Durodami J. Lisk, Ratibor Radojcic
  • Patent number: 8546923
    Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mold so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression molding compound into the mold while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
  • Patent number: 8536687
    Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiyuki Hata