Abstract: A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.

Abstract: In semiconductor devices, the alignment mark for performing alignment processes of measurement tools and the like may be positioned within the die seal area on the basis of a geometric configuration, which still preserves mechanical integrity of the die seal without compromising the spatial information encoded into the alignment marks. For example, L-shaped alignment marks may be provided at one or more corners of the die seal area.

Abstract: A box-in-box overlay mark is described, including an inner box region and an outer box region surrounding the same, dense narrow trenches in the previous layer in the inner box region and the outer box region, x- and y-directional linear photoresist patterns defining a rectangle over the narrow trenches in the inner box region, and x- and y-directional linear patterns defining another rectangle in the outer box region. At least the narrow trenches in the inner box region are orientated in a direction different from the x-direction and the y-direction. The linear photoresist patterns are defined in or from a photoresist layer for defining a current layer, each of which is wider than each of the narrow trenches. The linear patterns are defined in or from the previously layer, each of which is wider than each of the narrow trenches.

Abstract: A lithographic process is used to form a plurality of target structures (92, 94) distributed at a plurality of locations across a substrate and having overlaid periodic structures with a number of different overlay bias values distributed across the target structures. At least some of the target structures comprise a number of overlaid periodic structures (e.g., gratings) that is fewer than said number of different overlay bias values. Asymmetry measurements are obtained for the target structures. The detected asymmetries are used to determine parameters of a lithographic process. Overlay model parameters including translation, magnification and rotation, can be calculated while correcting the effect of bottom grating asymmetry, and using a multi-parameter model of overlay error across the substrate.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.

Abstract: Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

Abstract: A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.

Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.

Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.

Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.

Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.

Abstract: A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.

Abstract: A method of manufacturing a semiconductor device includes: forming a recessed portion in a semiconductor substrate; forming an insulating film in the recessed portion; after forming the insulating film, forming a silicide layer on the semiconductor substrate in contact with the insulating film; and performing alignment between an electron beam exposure apparatus and the semiconductor substrate by using the insulating film and the silicide layer as an alignment mark.

Abstract: A plurality of overlay errors in a structure is determined using a target that includes a plurality of diffraction based overlay pads. Each diffraction based overlay pad has the same number of periodic patterns as the structure under test. Additionally, each diffraction based overlay pad includes a programmed shift between each pair of periodic patterns. The pads are illuminated and the resulting light is detected and used to simultaneously determine the plurality of overlay errors in the structure based on the programmed shifts. The overlay errors may be determined using a subset of elements of the Mueller matrix or by using the resulting spectra from the pads.

Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

Abstract: An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements.

Abstract: A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.

Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.

Abstract: Sensor packages and methods for making a sensor device package for side mounting on a circuit board. A sensor device(s) in a mechanical layer of silicon is sandwiched between first and second layers of glass to create a wafer. A first via(s) is created in the first or second layers to expose a predefined area of the mechanical layer of silicon. A second via(s) is created in the first or second layers. The least one second via has a depth dimension that is less than a depth dimension of the first via. A metallic trace is applied between the exposed area on the mechanical layer and a portion of the second via. The wafer is sliced such that the second via is separated into two sections, thereby creating a sensor die. The sensor die is then electrically and mechanically bonded to a circuit board at the sliced second via.

Abstract: An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The length of the first feature is greater than the width of the first feature. The overlay mark also comprises a second feature in a second layer over the first layer. The second feature has a length extending in the second longitudinal direction and a width extending in the first longitudinal direction. The length of the second feature is greater than the width of the second feature. The overlay mark further comprises a third feature in a third layer over the second layer. The third feature is a box-shaped opening in the third layer.

Abstract: According to one embodiment, a semiconductor memory device includes an electrical terminal disposed in a first side; a first surface including a first part, a second part, and a third part, a mark of the semiconductor memory device being printed in the first part, the second part being disposed in a second side, the second side being opposite side of the first side, the third part being disposed around the first part, a first surface roughness of the first part being higher than a second surface roughness of the third part.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM horizontal and vertical positions at horizontal and vertical midpoints, respectively, of the first RX pad; providing a second RX pad abutting the first RX pad and a first STI pad abutting the second RX pad, each having a vertical midpoint at the SPM vertical position; forming a first gate alignment mark on the second RX pad and having vertical endpoints horizontally aligned with vertical endpoints of the second RX pad; and forming a second gate alignment mark on the first STI pad and having vertical endpoints horizontally aligned with vertical endpoints of the first STI pad.

Abstract: An integrated structure with a silicon-through via includes a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.

Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.

Abstract: A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling.

Abstract: Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.

Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.

Abstract: Alignment of layers during manufacture of a multi-layer sample is controlled by applying optical measurements to a measurement site in the sample. The measurement site includes two diffractive structures located one above the other in two different layers, respectively. The optical measurements include at least two measurements with different polarization states of incident light, each measurement including illuminating the measurement site so as to illuminate one of the diffractive structures through the other. The diffraction properties of the measurement site are indicative of a lateral shift between the diffractive structures. The diffraction properties detected are analyzed for the different polarization states of the incident light to determine an existing lateral shift between the layers.

Abstract: Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer by using a mask process to form a spacer and a contact hole filling layer, the contact hole filing layer is used for filling contact holes on the thin film transistor array substrate; forming an alignment film on the substrate patterning with the spacer and the contact hole filing layer.

Abstract: A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch.

Abstract: According to one embodiment, an alignment mark provided on an underlayer includes a plurality of first guide pattern features, and a first self-assembled film. The first guide pattern features extend in a first direction and are aligned in a second direction crossing the first direction. The first self-assembled film is provided between adjacent ones of the first guide pattern features and includes a plurality of first line pattern features and a second line pattern feature. The first line pattern features extends in the first direction, is aligned in the second direction, and has a pitch in the second direction narrower than a pitch in the second direction of the first guide pattern features. The second line pattern feature is provided between adjacent ones of the first line pattern features and extends in the first direction.

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

Abstract: A lithographic mask reticle includes a first mask region having a first mask pattern configured for use in fabrication of electronic circuit structures, and a second mask region having a second mask pattern configured for use in fabrication of test structures. The second mask pattern includes all categories of structural patterns containing in the first mask pattern.

Abstract: A method includes a first step of forming a circuit pattern and an alignment mark on a substrate and a second step of measuring a position of the alignment mark and positioning the substrate. The alignment mark includes a first linear pattern arranged on one side of a first straight line, a second linear pattern arranged on the other side of the first straight line, a third linear pattern arranged on one side of a second straight line, and a fourth linear pattern arranged on the other side of the second straight line. The first step includes determining total number of the third and fourth linear patterns to be formed and total number of the first and second linear patterns to be formed based on required precisions in directions along the first and second straight lines.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.

Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.

Abstract: A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.