Abstract: A geometric diode, method and device applications are described. The geometric diode is produced including a device body formed from an electrically conductive material having an equilibrium mobile charge density, and having a device surface configuration. The material has a charge carrier mean free path with a mean free path length and the device body size is selected based on said the free path length to serve as an electrically conductive path between first and second electrodes delimited by the device surface configuration that is asymmetric with respect to a forward flow of current in a forward direction from the first electrode to the second electrode as compared to a reverse current flow in an reverse direction from the second electrode to the first electrode. A system includes an antenna for receiving electromagnetic radiation coupled with the geometric diode antenna to receive the electromagnetic radiation to produce an electrical response.

Abstract: A semiconductor device includes a first pattern and a plurality of second patterns arranged at equal intervals. When the distance of the space between the first pattern and the second pattern closet to the first pattern is larger than a first distance, a plurality of dummy patterns are arranged in the space with shapes and intervals similar to those of the second patterns. When the distance of the space is equal to or less than the first distance and larger than a second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and extends toward the first pattern to be brought into contact with the first pattern. When the distance of the space is equal to or less than the second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and is connected to the first pattern.

Abstract: An ionic device includes a layer of an ionic conductor containing first and second species of impurities. The first species of impurity in the layer is mobile in the ionic conductor, and a concentration profile of the first species determines a functional characteristic of the device. The second species of impurity in the layer interacts with the first species within the layer to create a structure that limits mobility of the first species in the layer.

Abstract: Systems and methods for stacking a memory chip with respect to an integrated circuit (IC) chip are described. In the systems and methods, a plurality of like memory chips are stacked above one or more IC chip members of a family. The use of a plurality of like memory chips for the family may save costs and complications involved in designing, fabricating, and assembling memory chips of different sizes. The use of a plurality of the memory chips on a single IC chip can enable higher data transfer rates due to parallel data transmission.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: The present invention relates to a CO2 laser-transparent material having a mark on the surface thereof and the method for making the same. The method includes the following steps: providing a first substrate, which has a top surface and a bottom surface; providing a second substrate which has a top surface; putting the bottom surface of the first substrate on the top surface of the second substrate; irradiating a CO2 laser beam to the top surface of the second substrate by passing through the top surface and the bottom surface of the first substrate; and forming a mark on the bottom surface of the first substrate. The material of the mark is oxide of the second substrate or the same as the material of the second substrate. Whereby the cheap CO2 laser is utilized to form the mark on the first substrate, and the mark can be erased easily by a proper chemical for recycling the first substrate.

Abstract: A semiconductor device includes a wafer and a dicing saw tape that is laminated to a back surface of the wafer. An active surface of the wafer is opposite the back surface of the wafer. The semiconductor device further includes a lamination tape disposed in contact with the wafer. The lamination tape includes an under-film layer contacting the active surface of the wafer. The lamination tape further includes an adhesive layer contacting the under-film layer.

Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.

Abstract: A loadport for handling film frames is disclosed. The loadport is modular and substantially compatible with applicable standards regarding modular equipment. In particular, the load port is substantially interchangeable with loadports not adapted for handling film frames. The loadport has a compact shuttle for moving film frames and flexible alignment mechanisms for aligning film frames and cassettes of different configurations.

Abstract: The present invention is aimed to provide an adhesive for bonding a semiconductor which has high transparency and facilitates recognition of a pattern or position indication on the occasion of semiconductor chip bonding. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein the amount of the inorganic filler in the adhesive is 30 to 70% by weight, the inorganic filler contains a filler A having an average particle size of less than 0.1 ?m and a filler B having an average particle size of not less than 0.1 ?m and less than 1 ?m, and the weight ratio of the filler A to the filler B is 1/9 to 6/4. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein difference in refractive index is not more than 0.1 between the epoxy resin and the inorganic filler.

Abstract: A semiconductor device includes a supporting substrate; a semiconductor substrate that includes a first surface in which at least one layer is formed and a second surface that is positioned on an opposite side to the first surface, and is pasted to a surface of the supporting substrate with adhesive such that the first surface faces the supporting substrate side; a protective film that is formed on the second surface of the semiconductor substrate and on a surface of the adhesive extending outwardly from a region between the supporting substrate and the semiconductor substrate, and including a perimeter part that is positioned outside a perimeter part of the adhesive, and positioned inside a perimeter part of the supporting substrate; and an electrode material that is formed so as to be embedded in a penetration hole that penetrates the protective film and the semiconductor substrate.

Abstract: Chemical vapor deposition (CVD) systems and methods for forming layers on a substrate are disclosed. Embodiments of the system comprise a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining site isolation. Methods of forming layers on a substrate comprise forming a first layer from a precursor on a substrate in a CVD environment, contacting the substrate with plasma in a plasma environment, wherein the forming and contacting steps are performed in the unitary system and repeating the forming and contacting steps until a layer of desired thickness is formed. The forming and contacting steps can be performed to form devices having multiple distinct layers, such as Group III-V thin film devices.

Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.

Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.

Abstract: A dicing die bonding film including a bonding layer; and a pressure-sensitive adhesive layer adjoining the bonding layer, the pressure-sensitive adhesive layer having a storage modulus of about 400 to about 600 kPa at 25° C. and a peel strength of about 200 to about 350 mN/25 mm with respect to the bonding layer as measured according to KS-A-01107 standard.

Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.

Abstract: A nanowire device includes a nanowire having differently functionalized segments. Each of the segments is configured to interact with a species to modulate the conductance of a segment. The nanowire is grown from a single catalyst and the segments include a first segment at a non-linear angle from a second segment.

Abstract: Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.

Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

Abstract: A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

Abstract: A laminate including a supporting member which is light transmissive; a supported substrate supported by the supporting member; an adhesive layer provided on a surface of the supported substrate which surface faces toward the supporting member; and a release layer which is made of a fluorocarbon and is provided between the supporting member and the supported substrate, the release layer having a property that changes when it absorbs light coming through the supporting member.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.

Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Abstract: Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes.

Abstract: A Hall sensor has a P-type semiconductor substrate and a Hall sensing portion having a square shape and an N-type conductivity disposed on a surface of the semiconductor substrate. The Hall sensor includes Hall voltage output terminals having the same shape with each other, and control current input terminals having the same shape with each other. The Hall voltage output terminals are disposed at respective ones of four vertices of the Hall sensing portion. The control current input terminals include pairs of control current input terminals disposed at respective ones of the four vertices of the Hall sensing portion and arranged on both sides of respective ones of the Hall voltage output terminals in spaced apart relation from the Hall voltage output terminals so as to prevent electrical connection between the control current input terminals and the Hall voltage output terminals.

Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.

Abstract: The invention is related to a semiconductor chip, at-least also accomplished in a semiconductor installation, containing at-least also a long, relatively narrow semiconductor substrate transfer/processing tunnel-arrangement, wherein during its operation at-least also the taking place of successive semiconductor processings of the successive, typically uninterruptedly displacing semiconductor substrate-sections there through and whereby in a device behind its exit by means of dividing these successive semiconductor substrate-sections the accomplishing thereof.

Abstract: Provided is a method of manufacturing a metal oxide film to be formed through the following processes: a coating process of forming a coating film on a substrate by using a coating liquid for forming metal oxide film containing any of various organometallic compounds; a drying process of making the coating film into a dried coating film; and a heating process of forming an inorganic film from the dried coating film under an oxygen-containing atmosphere having a dew-point temperature equal to or lower than ?10° C.

Abstract: A curable composition, suitable for underfill encapsulant, has two distinct phase domains after cure, a continuous phase and a discontinuous phase, in which one phase has a modulus value of 2 GPa or greater, and the second phase has a modulus value at least 1 Gpa less than the first phase, characterized in that the phases are generated in situ as the composition cures.

Abstract: A positive tone photosensitive composition comprising: (A) an alkali-soluble resin having a phenolic hydroxyl group; (B) a phenol resin modified by a compound having an unsaturated hydrocarbon group containing 4 to 100 carbon atoms; (C) a compound that generates an acid by the action of light; (D) a thermal cross-linker that crosslinks the ingredient (A) and the ingredient (B) by heating; and (E) a solvent.

Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si?C, B, Si?B, Si?B?C, and B?C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.

Abstract: An arrangement comprising: at least one power semiconductor module and a transport packaging. The power semiconductor module has a base element, a housing and connection elements. The transport packaging has a cover layer, an interlayer with a respective cutout assigned to the power semiconductor module, and a cover film. The cover layer is generally planar, and has a first main surface facing the power semiconductor module. The interlayer is arranged on the first main surface of the cover layer. The power semiconductor module is arranged in the cutout, on the first main surface of the cover layer, wherein the base element of the power semiconductor module is disposed on the first main surface of the cover layer. The cover film bears on and covers substantial parts of the housing of the power semiconductor module. The cover film is connected to the first main surface of the interlayer.

Abstract: Disclosed is a method for surface-treating a semiconductor substrate to thereby reduce loss of minority carriers caused by surface recombination and improve the lifetime. In the method, a semiconductor substrate is prepared. An acid additive and an alkaline additive are added to water to obtain an aqueous solution having a pH of not more than 7. The aqueous solution comprises no hydrofluoric acid. A dangling bond at a surface of the semiconductor substrate is hydrogen-terminated. The surface, at which the dangling bond has been hydrogen-terminated, is brought into contact with the aqueous solution.

Abstract: An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.

Abstract: The adhesive composition of the invention comprises (A) a thermoplastic resin with a Tg of no higher than 100° C. and (B) a thermosetting component, wherein the (B) thermosetting component includes (B1) a compound with an allyl group and (B2) a compound with a maleimide group.

Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.

Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

Abstract: Provided is a method of forming a pattern, ensuring excellent exposure latitude (EL) and focus latitude (depth of focus DOF). The method of forming a pattern includes (A) forming a film from a resist composition, the resist composition, (B) exposing the film to light, and (C) developing the exposed film using a developer containing an organic solvent, thereby forming a negative pattern. The resist composition contains (a) a resin that is configured to decompose when acted on by an acid and ?SP thereof represented by formula (1) below is 2.5 (MPa)1/2 or above, (b) a compound that is composed to generate an acid when exposed to actinic rays or radiation, and (c) a solvent.

Abstract: A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device.

Abstract: Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile).

Abstract: A method of manufacturing a bonded body of a semiconductor substrate and a semiconductor device to be mounted on the semiconductor substrate are provided. The method includes: preparing a first base member and a second base member; imparting liquid repellency for a liquid material to at least a part of a bonding film non-formation region of the first base member to form a liquid repellent region thereon; supplying the liquid material onto the first base member to selectively form a liquid coating on a bonding film formation region of the first base member; drying the liquid coating to obtain a bonding film on the bonding film formation region; and bonding the first base member and the second base member together through the bonding film due to a bonding property developed in a vicinity of a surface of the bonding film to thereby obtain the bonded body.

Abstract: One aspect of the present invention provides a polymer having repeating units represented by the formulas (1-1), (1-2) and (1-3) and weight-average molecular weight of from 3,000 to 500,000, as determined by GPC using tetrahydrofuran as a solvent, reduced to polystyrene. Another aspect of the present invention provides an adhesive composition comprising (A) the polymer, (B) a thermosetting resin, and (C) a compound having flux activity. Further, the present invention provides an adhesive sheet having an adhesive layer made of the adhesive composition, a protective material for a semiconductor device, which has the adhesive layer, and a semiconductor device having a cured product obtained from the adhesive composition.

Abstract: A method for delineating a metallization pattern in a layer of sputtered aluminum or sputtered copper using a broad spectrum high intensity light source. The metal is deposited on a polymeric substrate by sputtering, so that it has a porous nanostructure. An opaque mask that is a positive representation of the desired metallization pattern is then situated over the metallization layer, exposing those portions of the metallization layer intended to be removed. The masked metallization layer is then exposed to a rapid burst of high intensity visible light from an arc source sufficient to cause complete removal of the exposed portions of the metallization layer, exposing the underlying substrate and creating the delineated pattern.

Abstract: A method and apparatus for obtaining inspection information is described. A standard CCD or CMOS camera is used to obtain images in the near infrared region. Background and noise components of the obtained image are removed and the signal to noise ratio is increased to provide information that is suitable for use in inspection.

Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).

Abstract: Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance.

Abstract: The present invention is aimed to provide an adhesive for bonding a semiconductor which has high transparency and facilitates recognition of a pattern or position indication on the occasion of semiconductor chip bonding. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein the amount of the inorganic filler in the adhesive is 30 to 70% by weight, the inorganic filler contains a filler A having an average particle size of less than 0.1 ?m and a filler B having an average particle size of not less than 0.1 ?m and less than 1 ?m, and the weight ratio of the filler A to the filler B is 1/9 to 6/4. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein difference in refractive index is not more than 0.1 between the epoxy resin and the inorganic filler.

Abstract: Disclosed is an adhesive composition used for adhesion of a semiconductor chip which contains a radiation polymerizable compound, a photoinitiator, and a thermosetting resin. When the adhesive composition forming an adhesive layer is brought to a B-stage by irradiation with light, the surface of the adhesive layer has a tack force of 200 gf/cm2 or less at 30° C. and 200 gf/cm2 or more at 120° C.