Active Layer Of Indirect Band Gap Semiconductor Patents (Class 257/86)
  • Patent number: 10692893
    Abstract: A substrate for a display device and a display device including the same are disclosed. The substrate includes a first thin-film transistor including an oxide semiconductor layer, a second thin-film transistor spaced apart from the first thin-film transistor and including a polycrystalline semiconductor layer, and a storage capacitor including at least two storage electrodes. One of the at least two storage electrodes is located in the same layer and is formed of the same material as a gate electrode of the second thin-film transistor that is disposed under the polycrystalline semiconductor layer, and another one of the at least two storage electrodes is located above the polycrystalline semiconductor layer with at least one insulation film interposed therebetween. Accordingly, lower power consumption and a larger area of the substrate are realized.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 23, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jong-Won Lee, Jeong-Oh Kim, Jung-Ho Bang
  • Patent number: 10651033
    Abstract: A method for manufacturing a semiconductor device structure is provided. The method includes providing a base substrate and forming a buffer layer on the base substrate. The method also includes forming a patterned silicon layer on the buffer layer. The patterned silicon layer has an opening to expose a portion of the buffer layer. The method further includes epitaxially growing a patterned channel layer and a patterned barrier layer on a top surface of the patterned silicon layer sequentially. In addition, the method includes forming a gate electrode on the patterned barrier layer.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 12, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Chou, Hsin-Chih Lin, Yu-Chieh Chou
  • Patent number: 10634944
    Abstract: To provide a method of manufacturing an optical film formed on a plastic substrate. There is provided a method of manufacturing an optical film including the steps of laminating a separation layer and an optical filter on a first substrate, separating the optical filter from the first substrate, attaching the optical filter to a second substrate. Since the optical film manufactured according to the invention has flexibility, it can be provided on a portion or a display device having a curved surface. Further, the optical film is not processed at high temperatures, and hence, an optical film having high yield with high reliability can be formed. Furthermore, an optical film having an excellent impact resistance property can be formed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akio Yamashita, Yumiko Ohno, Yuugo Goto
  • Patent number: 10490758
    Abstract: The present invention provides a flexible organic light-emitting diode (OLED) display panel, which includes a first polyimide layer, a barrier layer and a second polyimide layer that are sequentially stacked and a thin film transistor (TFT) structure and an OLED structure that are sequentially disposed on the second polyimide layer, in which a material of the barrier layer includes at least one of silicon dioxide and silicon nitride. By arranging a flexible base as an upper polyimide layer and a lower polyimide layer and adding a barrier layer between the two polyimide layers, the present invention can effectively block water and oxygen from entering an interior of a component through a flexible polyimide base, thereby protecting the TFT structure and the OLED structure and improving the lifespan of the OLED display panel. The present invention further provides a manufacturing method of a flexible OLED display panel.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 26, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Rui Xie
  • Patent number: 10263140
    Abstract: The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 16, 2019
    Inventor: Sang Jeong An
  • Patent number: 10153393
    Abstract: A light emitting diode including an n-doped InXnGa(1-Xn)N layer and a p-doped InXpGa(1-Xp)N layer, and an active area arranged between the InXnGa(1-Xn)N layer and the InXpGa(1-Xp)N layer including: a first InN layer with a thickness eInN106; a second InN layer with a thickness eInN108; a separating layer arranged between the InN layers and including InXbGa(1-Xb)N and a thickness <3 nm; an InX1Ga(1-X1)N layer arranged between the InXnGa(1-Xn)N layer and the first InN layer; an InX2Ga(1-X2)N layer arranged between the InXpGa(1-Xp)N layer and the second InN layer; wherein the indium compositions Xn, Xp, Xb, X1 and X2 are between 0 and about 0.25, and wherein the thicknesses eInN106 and eInN108 are such that eInN106<eInN108.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: December 11, 2018
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, ALEDIA
    Inventors: Ivan-Christophe Robin, Amelie Dussaigne
  • Patent number: 10109770
    Abstract: A light emitting diode includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure out from the top of the epitaxial structure. A method for manufacturing the light emitting diode is also presented. The light emitting diode and the method increase lighting efficiency of the light emitting diode.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 23, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC
    Inventors: Ching-Hsueh Chiu, Chia-Hung Huang, Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang
  • Patent number: 10062775
    Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 28, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Sen Huang, Xinyu Liu, Xinhua Wang, Ke Wei, Qilong Bao, Wenwu Wang, Chao Zhao
  • Patent number: 9929307
    Abstract: The present invention provides a light emitting device which emit light having a high-order level without increasing a current injection density to an active layer. A light emitting device according to the present invention includes an upper electrode layer, a lower electrode layer, and an active layer provided between them. In this case, light is emitted by injection of electric current to the active layer through the upper electrode layer and the lower electrode layer, the active layer has a plurality of quantum-confined structures, and a first quantum-confined structure has a ground level having an energy level E0 and a high-order level having an energy level E1, and a second quantum-confined structure has an energy level E2 which is higher than the E0, and the E1 and the E2 are substantially matched.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 27, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Uchida, Takeshi Yoshioka
  • Patent number: 9647224
    Abstract: Provided is a method for manufacturing an organic EL device, including: a vapor deposition step of forming an organic layer over a substrate moving relative to a nozzle by discharging a vaporized organic layer-forming material through the nozzle. The vapor deposition step is performed so that a light emitting region formed of the organic layer and having a width A (mm) in a direction perpendicular to a direction in which the substrate is moving is formed, and so that W?A+2×h (where h?5 mm) is satisfied, where a length of an opening of the nozzle in the direction perpendicular to the direction in which the substrate is moving is denoted by W (mm), and a distance between the opening and the substrate is denoted by h (mm).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 9, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Ryohei Kakiuchi, Shigenori Morita, Kanako Hida
  • Patent number: 9647210
    Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
  • Patent number: 9515264
    Abstract: A method for manufacturing a display device is provided. The method includes: forming, between a first substrate and a second substrate, a light-emitting element including an electroluminescence layer and a wiring over which a peeling layer formed by using the material of the electroluminescence layer is provided; and peeling whole of the second substrate from the first substrate so that the peeling layer over the wiring is simultaneously exposed.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Sakuishi, Daiki Nakamura, Akihiro Chida, Tomoya Aoyama
  • Patent number: 9508930
    Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
  • Patent number: 9461202
    Abstract: This invention provides a high-efficiency light-emitting device and the manufacturing method thereof The high-efficiency light-emitting device includes a substrate; a reflective layer; a bonding layer; a first semiconductor layer; an active layer; and a second semiconductor layer formed on the active layer. The second semiconductor layer includes a first surface having a first lower region and a first higher region.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: October 4, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Ming Chuang, Donald Tai-Chan Huo, Chia-Chen Chang, Tzu-Ling Yang, Chen Ou
  • Patent number: 9425359
    Abstract: A light emitting diode includes a semiconductor stacked structure, a substrate, a first electrode, a second electrode and a third electrode. The semiconductor stacked structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. An undoped semiconductor layer over the first semiconductor layer may be not removed or not completely removed to increase the strength of the semiconductor stacked structure and improve the reliability of the LED and the production yields of manufacturing process. A roughened structure (or a photonic crystal) can be formed on the undoped semiconductor layer when the semiconductor stacked structure to improve the light emitting efficiency of the LED.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 23, 2016
    Assignees: Industrial Technology Research Institute, TYNTEK CORPORATION
    Inventors: Yao-Jun Tsai, Shih-Yi Wen, Chen-Peng Hsu, Hung-Lieh Hu, Chia-Chun Yu, Yen-Chu Li, Chun-Yi Tung
  • Patent number: 9178178
    Abstract: Provided is an organic light-emitting diode (OLED) display including: first and second plastic layers; a first barrier layer and a first intermediate layer each positioned between the first and second plastic layers; and an OLED layer formed on the second plastic layer. The first barrier layer comprises silicon nitride.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Seob Lee, Yong-Hwan Park
  • Patent number: 9136344
    Abstract: A method of manufacturing a semiconductor device includes grinding a back side of a substrate; and forming a nitride semiconductor layer on a front side of the substrate after the grinding. Compressive stress is generated in the nitride semiconductor layer that is formed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 15, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Shuichi Tomabechi
  • Patent number: 9136427
    Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 15, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Kwang Joong Kim, Chang Suk Han, Kyung Hee Ye, Seung Kyu Choi, Ki Bum Nam, Nam Yoon Kim, Kyung Hae Kim, Ju Hyung Yoon
  • Patent number: 9117970
    Abstract: A light emitting device (10) comprises a body (11) comprising a substrate (12) of a p-type semiconductor material. The substrate has an upper surface (14) and having formed therein on one side of the upper surface and according to a bulk semi-conductor fabrication process utilizing lateral active area isolation techniques: a first n+-type island (16) to form a first junction (24) between the first island and the substrate; and a second n+-type island (18) spaced laterally from the first island (16). The substrate provides a laterally extending link (20) between the islands having an upper surface. The upper surface of the link, an upper surface of the island (16) and an upper surface of the island (18) collectively form a planar interface (21) between the body (11) and an isolation layer (19) of the device. The device comprises a terminal arrangement to apply a reverse bias to the first junction, to cause the device to emit light. The device is configured to facilitate the transmission of the emitted light.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 25, 2015
    Assignee: INSIAVA (PTY) LIMITED
    Inventor: Petrus Johannes Venter
  • Patent number: 9082891
    Abstract: A method for manufacturing a deep isolation trench (221) and a method for manufacturing a high-voltage LED chip. Steps of the method for manufacturing a deep isolation trench (221) are as follows: forming a mask layer (202) on a substrate (200), and forming, in the mask layer, through etching, multiple windows (204) isolated from each other, the bottom of each window exposing the substrate; with epitaxial lateral overgrowth, forming an epitaxial structure (212) inside each window and a part of the mask layer around the window, respectively, each epitaxial structure having a trapezoidal cross section with a long bottom and a short top, and a gap between adjacent epitaxial structures forming a first deep trench (214); etching each epitaxial structure, forming a first shoulder (218) and a second shoulder (221) at both sides of each epitaxial structure, respectively, and forming a deep isolation trench above the mask layer between the adjacent epitaxial structures.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 14, 2015
    Assignee: ENRAYTEK OPTOELECTRONICS CO., LTD.
    Inventors: Lujun Yao, Deyuan Xiao, Richard Ru-Gin Chang, Hongbo Yu
  • Patent number: 9076928
    Abstract: A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Seok Yang, Ki Seok Kim, Je Won Kim, Ju Bin Seo, Sang Seok Lee, Joon Sub Lee, Jin Bock Lee
  • Patent number: 9048385
    Abstract: In a nitride semiconductor light emitting diode including a substrate made of a nitride semiconductor, a first conductive-type nitride semiconductor layer formed on the substrate, an active layer made of a nitride semiconductor, and a second conductive-type nitride semiconductor layer, characterized in that light emitted is extracted from the under surface side of the substrate or the upper surface side of the second conductive-type nitride semiconductor layer, an intermediate layer is formed between the substrate and the active layer, and dislocations is allowed to generates from the dislocation generating layer as the origin and to distribute in a light emitting region of the active layer.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: June 2, 2015
    Assignee: NICHIA CORPORATION
    Inventor: Daisuke Sanga
  • Patent number: 9034685
    Abstract: The present invention provides methods for making pnictide compositions, particularly photoactive and/or semiconductive pnictides. In many embodiments, these compositions are in the form of thin films grown on a wide range of suitable substrates to be incorporated into a wide range of microelectronic devices, including photovoltaic devices, photodetectors, light emitting diodes, betavoltaic devices, thermoelectric devices, transistors, other optoelectronic devices, and the like. As an overview, the present invention prepares these compositions from suitable source compounds in which a vapor flux is derived from a source compound in a first processing zone, the vapor flux is treated in a second processing zone distinct from the first processing zone, and then the treated vapor flux, optionally in combination with one or more other ingredients, is used to grow pnictide films on a suitable substrate.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 19, 2015
    Assignees: Dow Global Technologies LLC, California Institute of Technology
    Inventors: Gregory M. Kimball, Jeffrey P. Bosco, Harry A. Atwater, Nathan S. Lewis, Marty W. Degroot, James C. Stevens
  • Patent number: 9029908
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9029875
    Abstract: Disclosed are a light emitting device, a method for manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer comprising a well layer and a barrier layer on the first conductive layer, and a second conductive semiconductor layer on the active layer. The well layer includes a first well layer closest to the first conductive semiconductor layer and having a first energy bandgap, a third well layer closest to the second conductive semiconductor layer and having a third energy bandgap, and a second well layer interposed between the first and third well layers and having a second energy bandgap. The third energy bandgap of the third well layer is greater than the second energy bandgap of the second well layer.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jong Ho Na, Se Hwan Sim, Chong Cook Kim, Jae In Yoon, Jong Pil Jeong, Jung Hyun Hwang, Dong Han Yoo
  • Patent number: 9018641
    Abstract: A method for manufacturing a radiation-emitting component (1) in which a field distribution of a near field (101, 201) in a direction perpendicular to a main emission axis of the component is specified. From the field distribution of the near field, an index of refraction profile (111, 211, 511) along this direction is determined. A structure is determined for the component such that the component will have the previously determined index of refraction profile. The component is constructed according to the previously determined structure. A radiation-emitting component is also disclosed.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: April 28, 2015
    Assignee: CSRAM Opto Semiconductors GmbH
    Inventors: Peter Brick, Uwe Strauss
  • Patent number: 9012886
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Alx1Ga1-x1N (0.1?x1?0.35).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Shinji Saito, Rei Hashimoto, Shinya Nunoue
  • Patent number: 8994055
    Abstract: A light source capable of solving a problem in which the etendue is increased when random polarization is converted into a specific polarization is provided. A relief structure that functions as surface plasmon excitation means for exciting a surface plasmon by a specific polarization component in a polarization direction perpendicular to a first direction in an interface between metal layer 15 and first cover layer 14 in light from emission layer 13 incident on the interface is formed at the interface. The relief structure is periodic in a second direction. Projections 21A of the relief structure are extended along the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 31, 2015
    Assignee: NEC Corporation
    Inventors: Shin Tominaga, Masao Imai, Masanao Natsumeda
  • Patent number: 8987757
    Abstract: Disclosed are a light emitting device and a lighting system having the same. The light emitting device includes a first conductivity-type semiconductor layer, an interfacial layer including at least two superlattice structures adjacent to the first conductivity-type semiconductor layer, an active layer adjacent to the interfacial layer, and a second conductivity-type semiconductor layer adjacent to the active layer. The first conductivity-type semiconductor layer, interfacial layer, active layer, and second conductivity-type semiconductor layer are stacked in a same direction, the first and second semiconductor layer are of different conductivity types, an energy band gap of the superlattice structure adjacent to the active layer is smaller than an energy band gap of the superlattice structure adjacent to the first conductivity-type semiconductor layer.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yong Tae Moon, Dae Seob Han, Jeong Sik Lee
  • Patent number: 8987024
    Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: Bridgelux, Inc
    Inventor: Tao Xu
  • Patent number: 8981388
    Abstract: Provided are a solar cell and a method of manufacturing the same. The method includes: preparing a bottom substrate including sequentially stacked first and second portions, each of the first and second portions including a plurality of grains, wherein the maximum grain size of the second portion is less than the minimum grains size of the first portion; exposing the first portion of the bottom substrate by removing the second portion of the bottom substrate; and forming a photovoltaic conversion layer on the first portion of the bottom substrate.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 17, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Hogyeong Yun
  • Publication number: 20150048387
    Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.
    Type: Application
    Filed: June 4, 2014
    Publication date: February 19, 2015
    Applicant: Georgetown University
    Inventors: Makarand PARANJAPE, Paola BARBARA, Amy LIU, Marcio FONTANA
  • Patent number: 8952364
    Abstract: Light-emitting devices are described herein.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Nitto Denko Corporation
    Inventors: Qianxi Lai, Shijun Zheng, David T. Sisk, Amane Mochizuki
  • Patent number: 8928009
    Abstract: A light emitting device includes: one or plural light emitting elements having plural electrodes; a chip-like insulator surrounding the one or plural light emitting elements from a side surface side of the one or plural light emitting elements; and plural terminal electrodes electrically connected one-to-one with the plural electrodes, and having protrusions each protruding from a peripheral edge of the chip-like insulator.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 6, 2015
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Katsuhiro Tomoda, Naoki Hirao
  • Patent number: 8916857
    Abstract: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which the first layer comprising a hole-transporting material is doped with a hole-blocking material or an organic compound having a large dipole moment. This structure allows the formation of a high performance light-emitting element with high luminous efficiency and long lifetime. The device structure of the present invention facilitates the control of the rate of the carrier transport, and thus, leads to the formation of a light-emitting element with a well-controlled carrier balance, which contributes to the excellent characteristics of the light-emitting element of the present invention.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Satoshi Seo, Ryoji Nomura
  • Patent number: 8901551
    Abstract: A light emitting diode (LED) structure including a substrate, a polymer layer, and an epitaxy layer is provided. The polymer layer is disposed on the substrate, wherein the polymer layer has a chemical formula of: wherein M represents sodium, zinc, magnesium, or potassium. The epitaxy layer is disposed on the polymer layer. The epitaxy layer is bonded to the substrate via the polymer layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 2, 2014
    Assignee: Genesis Photonics Inc.
    Inventors: Kuan-Chieh Huang, Tung-Lin Chuang
  • Patent number: 8896020
    Abstract: Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm?2 or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 25, 2014
    Assignee: Crystal IS, Inc.
    Inventors: Leo Schowalter, Glen A. Slack, Juan Carlos Rojo, Robert T. Bondokov, Kenneth E. Morgan, Joseph A. Smart
  • Patent number: 8890177
    Abstract: An electronic or optoelectronic device fabricated from a crystalline material in which a parameter of a bandgap characteristic of said crystalline material has been modified locally by introducing distortions on an atomic scale in the lattice structure of said crystalline material and the electronic and/or optoelectronic parameters of said device are dependent on the modification of said bandgap is exemplified by a radiation emissive optoelectronic semiconductor device which comprises a junction (10) formed from a p-type layer (11) and an n-type layer (12), both formed from indirect bandgap semiconductor material. The p-type layer (11) contains a array of dislocation loops which create a strain field to confine spatially and promote radiative recombination of the charge carriers.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 18, 2014
    Assignee: University of Surrey
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam, Guosheng Shao
  • Patent number: 8853735
    Abstract: Provided is an epitaxial substrate for a semiconductor device, which has excellent schottky contact characteristics that are stable over time. The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer formed of a first group III nitride containing at least Ga and having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1), and a barrier layer formed of a second group III nitride containing at least In and Al and having a composition of Inx2Aly2Gaz2N (x2+y2+z2=1), wherein the barrier layer has tensile strains in an in-plane direction, and pits are formed on a surface of the barrier layer at a surface density of 5×107/cm2 or more and 1×109/cm2 or less.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: October 7, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Patent number: 8847206
    Abstract: Disclosed is a surface modifying agent including a compound having an ethynyl group at one terminal end, a laminated structure manufactured using the surface modifying agent, a method of manufacturing the laminated structure, and a transistor including the same.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-il Park, Byung-wook Yoo, Do-hwan Kim, Sang-yoon Lee, Bang-lin Lee, Eun-jeong Jeong
  • Publication number: 20140284631
    Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.
    Type: Application
    Filed: June 4, 2014
    Publication date: September 25, 2014
    Inventors: Makarand PARANJAPE, Paola BARBARA, Amy LIU, Marcio FONTANA
  • Patent number: 8835973
    Abstract: Light-emitting elements in which an increase of driving voltage can be suppressed are provided. Light-emitting devices whose power consumption is reduced by including such light-emitting elements are also provided. In a light-emitting element having an EL layer between an anode and a cathode, a first layer in which carriers can be produced is formed between the cathode and the EL layer and in contact with the cathode, a second layer which transfers electrons produced in the first layer is formed in contact with the first layer, and a third layer which injects the electrons received from the second layer into the EL layer is formed in contact with the second layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromi Nowatari, Satoshi Seo, Nobuharu Ohsawa, Tetsuo Tsutsui
  • Patent number: 8829491
    Abstract: According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-won Lee, Jun-youn Kim, Young-jo Tak
  • Patent number: 8766330
    Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 1, 2014
    Assignee: Georgetown University
    Inventors: Makarand Paranjape, Paola Barbara, Amy Liu, Marcio Fontana
  • Patent number: 8759845
    Abstract: A light emitting device (10) comprises a body (12) of a semiconductor material. A first junction region (14) is formed in the body between a first region (12.1) of the body of a first doping kind and a second region (12.2) of the body of a second doping kind. A second junction region (16) is formed in the body between the second region (12.2) of the body and a third region (12.3) of the body of the first doping kind. A terminal arrangement (18) is connected to the body for, in use, reverse biasing the first junction region (14) into a breakdown mode and for forward biasing at least part (16.1) of the second junction region (16), to inject carriers towards the first junction region (14). The device (10) is configured so that a first depletion region (20) associated with the reverse biased first junction region (14) punches through to a second depletion region associated with the forward biased second junction region (16).
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: June 24, 2014
    Assignee: Insiava (Pty) Limited
    Inventors: Lukas Willem Snyman, Monuko Du Plessis
  • Patent number: 8754528
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a crystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Maki Sugai, Eiji Muramoto, Shinya Nunoue
  • Patent number: 8748908
    Abstract: A semiconductor optical emission device comprising a layer of material containing a plurality of stress variations and adhering to a surface of a semiconductor is described. In one embodiment the semiconductor is an indirect band gap semiconductor and is silicon in one aspect, the material of the layer comprises silicon and metal oxides and is prepared by a sol-gel process including thermal annealing in one aspect. The layer urges a plurality of randomly distributed elastic deformations in the semiconductor that substantially enhances the radiative recombination interactions among free carriers in the semiconductor.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: June 10, 2014
    Inventors: Sufian Abedrabbo, Anthony Thomas Fiory
  • Patent number: 8723336
    Abstract: According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuharu Sugawara
  • Patent number: 8716693
    Abstract: A light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system are disclosed. The light emitting device may include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers. The first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer may include Al. The second conductive semiconductor layer may have Al content higher than Al content of the first conductive semiconductor layer. The first conductive semiconductor layer may have Al content higher than Al content of the active layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: May 6, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8698145
    Abstract: In an organic light-emitting display device and a method of manufacturing the same, the organic light-emitting display device comprises: an active layer of a thin film transistor which includes a semiconductor material, and which is formed on a substrate; a lower electrode of a capacitor which includes a semiconductor material doped with ion impurities, and which is formed on the substrate; a first insulating layer formed on the substrate so as to cover the active layer and the lower electrode; a first gate electrode which is a transparent conductive material, and which is formed on the first insulating layer; a second gate electrode which is a metal, and which is formed on the first gate electrode; an upper electrode of a capacitor which is formed on the first insulating layer and includes a transparent conductive material; source and drain electrodes of a thin film transistor which are electrically connected to the active layer; a pixel electrode formed on the first insulating layer, which is a semi-permeab
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sung-Ho Kim