Abstract: Embodiments of the present disclosure include nanowire field-effect transistors, systems for temperature history detection, methods for thermal history detection, a matrix of field effect transistors, and the like.

Abstract: A semiconductor phosphor nanoparticle includes a semiconductor nanoparticle and a first organic compound. An end of the first organic compound is bonded to a surface of the semiconductor nanoparticle, and the other end of the first organic compound is polymerized to form a first inorganic layer.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.

Abstract: A junctionless Nano-Electro-Mechanical (NEM) resonator, comprising a highly doped conductive channel connecting a drain region and a source region; the conduction channel region is movable and the overall structure is fixed at least at these two ends placed on acting the source and drain regions, respectively; at least one fixed gate electrode arranged to control a depletion charge in the highly doped conductive channel thereby modulating dimensions of a cross-section of the highly doped conductive channel. A dimension of the cross-section in the direction of an electrical field that is oriented from the fixed gate electrode to the highly doped conductive channel, is designed in such a way that it can be reduced under the effect of the depletion charge such that a full depletion in the highly doped conductive channel is achievable with the control of the fixed gate electrode.

Abstract: A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode.

Abstract: Various examples are provided for pillar array photo detectors. In one example, among others, a photo detection system includes an array of substantially aligned photo sensitive nanorods extending between first and second electrodes, and a plurality of resistance monitoring circuits coupled at different positions about the circumference of the electrodes. In another example, a photo detector includes first and second electrodes, and an array of substantially aligned photo sensitive nanorods extending between the substantially parallel electrodes. Light passing through an electrode excites electrons in the photo sensitive nanorods that are illuminated by the light.

Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.

Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0<x<1, 0<y<2. Values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi. The magnetically doped TI quantum well film is in 3 QL to 5 QL.

Abstract: A graphene nanomesh includes a sheet of graphene having a plurality of periodically arranged apertures, wherein the plurality of apertures have a substantially uniform periodicity and substantially uniform neck width. The graphene nanomesh can open up a large band gap in a sheet of graphene to create a semiconducting thin film. The periodicity and neck width of the apertures formed in the graphene nanomesh may be tuned to alter the electrical properties of the graphene nanomesh. The graphene nanomesh is prepared with block copolymer lithography. Graphene nanomesh field-effect transistors (FETs) can support currents nearly 100 times greater than individual graphene nanoribbon devices and the on-off ratio, which is comparable with values achieved in nanoribbon devices, can be tuned by varying the neck width. The graphene nanomesh may also be incorporated into FET-type sensor devices.

Abstract: A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.

Abstract: A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided. It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises: an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; and a gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.

Abstract: A nanowire device and a method of making a nanowire device are provided. The device includes a plurality of nanowires functionalized with different functionalizing compounds. The method includes functionalizing the nanowires with a functionalizing compound, dispersing the nanowires in a polar or semi-polar solvent, aligning the nanowires on a substrate such that longitudinal axes of the nanowires are oriented about perpendicular to a major surface of the substrate, and fixing the nanowires to the substrate.

Abstract: A magnetic element is disclosed wherein first and second interfaces of a free layer with a Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to lower switching current or increase thermal stability in a magnetic tunnel junction (MTJ). In a MTJ with a bottom spin valve configuration where the Hk enhancing layer is an oxide, the capping layer contacting the Hk enhancing layer is selected to have a free energy of oxide formation substantially greater than that of the oxide. The free layer may be a single layer or composite comprised of an Fe rich alloy such as Co20Fe60B20. With a thin free layer, the interfacial perpendicular anisotropy may dominate the shape anisotropy to generate a magnetization perpendicular to the planes of the layers. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device.

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: A photodetector 1A comprises an optical element 10, having a structure including first regions and second regions periodically arranged with respect to the first regions along a plane perpendicular to a predetermined direction, for generating an electric field component in the predetermined direction when light is incident thereon along the predetermined direction; and a semiconductor multilayer body 4 having a quantum cascade structure, arranged on the other side opposite from one side in the predetermined direction with respect to the optical element, for producing a current according to the electric field component in the predetermined direction generated by the optical element 10; while the quantum cascade structure includes an active region 4b for exciting an electron and an injector region 4c for transporting the electron, the active region 4b being formed on the outermost surface on the one side of the injector region 4c in the quantum cascade structure.

Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.

Abstract: A curing device may comprise a first array of LED's, each LED of the first array emitting radiation substantially centered at a first excitation wavelength onto a quantum dot layer, the quantum dot layer positioned above the first array of LED's and configured to partially absorb the first excitation wavelength radiation and down convert the absorbed first excitation wavelength radiation, and partially transmit the emitted first excitation wavelength radiation, wherein the down converted and the partially transmitted first excitation wavelength radiation are directed onto a radiation-curable workpiece.

Abstract: A system includes a semiconductor substrate having at least two electrodes disposed thereon, a dielectric layer disposed over the electrodes, a graphene layer disposed over the dielectric layer and electrically isolated from the electrodes, and a differential amplifier operatively connected to the electrodes and electrically isolated from the graphene layer. A radiation-sensitive layer may be disposed over the graphene layer and a voltage source may be operatively connected to two of the electrodes. The system may be contained on an integrated circuit and may be used to sense radiation in liquid and gas form.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: An optical-microwave-quantum transducer can include a tapered optical fiber configured to transmit and receive optical signals. The optical-microwave-quantum transducer can also include a cantilever that can include an optical cavity that includes a nanophotonic crystal. The optical cavity can be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons emitted from the tapered optical fiber. The cantilever can also include a mechanical coupler that is configured to induce electrical modulation onto a superconducting cavity in response to the mechanical excitation. The mechanical coupler can also be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons from the superconducting cavity. The optical cavity can further be configured to provide electromagnetic excitation that induces optical modulation on the tapered optical fiber in response to the mechanical excitation.

Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

Abstract: The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa.

Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.

Abstract: In an embodiment, a transistor arrangement is provided. The transistor arrangement comprises a nanowire including a first nanowire region and a second nanowire region; a first gate contact disposed over the first nanowire region; an insulating region disposed over the second nanowire region; a second gate contact disposed over the insulating region; wherein the first nanowire region and the first gate contact forms a part of an enhancement mode transistor and the second nanowire region, the insulating region and the second gate contact forms a part of a depletion mode transistor. A method of forming a transistor arrangement may also be provided. Also contemplated is a transistor and a method for forming said transistor, where the transistor comprises a nanowire and a gate contact, where the gate contact is formed by directly writing the gate contact onto a region of the nanowire.

Abstract: Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: A multi junction photovoltaic cell for converting light into electrical energy, comprising a substrate (3) having a surface (31), wherein a region (4) at the surface (31) of the substrate (3) is doped such that a first p-n junction is formed in the substrate (3). The photovoltaic cell has a nanowire (2) that is arranged on the surface (31) of the substrate (3) at a position where the doped region (4) is located in the substrate (3), such that a second p-n junction is formed at the nanowire (2) and in series connection with the first p-n junction.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire.

Abstract: Room temperature IR and UV photodetectors are provided by electrochemical self-assembly of nanowires. The detectivity of such IR detectors is up to ten times better than the state of the art. Broad peaks are observed in the room temperature absorption spectra of 10-nm diameter nanowires of CdSe and ZnS at photon energies close to the bandgap energy, indicating that the detectors are frequency selective and preferably detect light of specific frequencies. Provided is a photodetector comprising: an aluminum substrate; a layer of insulator disposed on the aluminum substrate and comprising an array of columnar pores; a plurality of semiconductor nanowires disposed within the pores and standing vertically relative to the aluminum substrate; a layer of nickel disposed in operable communication with one or more of the semiconductor nanowires; and wire leads in operable communication with the aluminum substrate and the layer of nickel for connection with an electrical circuit.

Abstract: The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

Abstract: Disclosed is a substrate-mediated assembly for graphene structures. According to an embodiment, long-range ordered, multilayer BN(111) films can be formed by atomic layer deposition (ALD) onto a substrate. The subject BN(111) films can then be used to order carbon atoms into a graphene sheet during a carbon deposition process.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A method for manufacturing a semiconductor nano layer structure includes: two substrates are provided; a plurality of semiconductor nanowires are formed on one of the substrates; an absorption surface is formed on the other substrate; one of the substrates is fixed on a cylindrical roller, the cylindrical roller is brought into contact with a surface of the substrate which is stationary and is not fixed on the cylindrical roller, and rolled with a constant velocity and pressure so that the semiconductor nanowires are break, detached, transferred and absorbed, and a semiconductor nano layer structure is formed on the stationary substrate; a de-laminating process is performed to separate the semiconductor nano layer structure from the second substrate; an electric Joule heat welding process is locally performed to bond each of the semiconductor nanowires of the semiconductor nano layer structure or each semiconductor nano layer structure.

Abstract: The present invention provides practical methods for n-type doping of graphene, either during graphene synthesis or following the formation of graphene. Some variations provide a method of n-type doping of graphene, comprising introducing a phosphorus-containing dopant fluid to a surface of graphene, under effective conditions to dope the graphene with phosphorus atoms or with phosphorus-containing molecules or fragments. It has been found that substitutional doping with phosphine can effectively modulate the electrical properties of graphene, such as graphene supported on Si or SiC substrates. Graphene sheet resistances well below 200 ohm/sq, and sheet carrier concentrations above 5×1013 cm?2, have been observed experimentally for n-doped graphene produced by the disclosed methods. This invention provides n-doped graphene for various electronic-device applications.

Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.

Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanaotubes.

Abstract: This invention is to provide a nanodevice, which is combined with an electronic device such as a diode, tunnel device and MOS transistor, integrated circuit and manufacturing method of the nanodevice. A nanodevice includes: a first insulating layer 2; one electrode 5A and the other electrode 5B provided to have a nanogap on the first insulating layer 2; a metal nanoparticle or a functional molecule provided between the one electrode 5A and the other electrode 5B; a second insulating layer 8 provided on the first insulating layer 2, and on the one electrode 5A and the other electrode 5B to embed the metal nanoparticle or the functional molecule. The second insulating layer works as a passivating layer.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.