Active Material Comprising Organic Conducting Material, E.g., Conducting Polymer (epo) Patents (Class 257/E21.007)
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Patent number: 8697579Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.Type: GrantFiled: January 31, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Sung Park, Se-Myeong Jang, Gil-Sub Kim
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Patent number: 8669187Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A layer, with porosities typically larger than the film thickness is provided where no film is desired. The film is applied over the porous layer and also where it is desired. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities that have arisen due to the film not bridging the spaces between solid portions. Etchant attacks both film surfaces. Particles may have diameters of four to ten times the film thickness. Particles may be silica, alumina and ceramics. Porous layers can be used in depressions or on flat surfaces.Type: GrantFiled: May 7, 2010Date of Patent: March 11, 2014Assignee: 1366 Technologies, Inc.Inventors: Emanuel M. Sachs, Andrew M. Gabor
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Patent number: 8664040Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.Type: GrantFiled: December 20, 2011Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng
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Patent number: 8647988Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: March 4, 2013Date of Patent: February 11, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8637113Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.Type: GrantFiled: January 19, 2012Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu, John Smythe, Bhaskar Srinivasan
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Patent number: 8633116Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.Type: GrantFiled: January 25, 2011Date of Patent: January 21, 2014Assignee: Ulvac, Inc.Inventors: Manabu Yoshii, Kazuhiro Watanabe
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Patent number: 8629567Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.Type: GrantFiled: December 15, 2011Date of Patent: January 14, 2014Assignee: Stats Chippac Ltd.Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
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Patent number: 8581421Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.Type: GrantFiled: December 16, 2011Date of Patent: November 12, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
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Patent number: 8546262Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.Type: GrantFiled: June 14, 2012Date of Patent: October 1, 2013Assignee: Sony CorporationInventors: Akiko Ogino, Yukihiro Sayama, Takayuki Shoya, Masaya Shimoji
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Patent number: 8541257Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.Type: GrantFiled: September 22, 2010Date of Patent: September 24, 2013Assignee: Cambridge University Technical Services LimitedInventors: Henning Sirringhaus, Richard Henry Friend, Richard John Wilson
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Patent number: 8536031Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: GrantFiled: February 19, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Patent number: 8530360Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 25, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventor: Abram M. Castro
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Patent number: 8525304Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.Type: GrantFiled: May 18, 2011Date of Patent: September 3, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
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Patent number: 8513680Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.Type: GrantFiled: September 16, 2011Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
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Patent number: 8476719Abstract: Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.Type: GrantFiled: May 18, 2011Date of Patent: July 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
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Patent number: 8455314Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.Type: GrantFiled: May 27, 2011Date of Patent: June 4, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
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Patent number: 8445919Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.Type: GrantFiled: February 19, 2010Date of Patent: May 21, 2013Assignee: China Wafer Level CSP LtdInventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
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Patent number: 8436439Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.Type: GrantFiled: August 30, 2010Date of Patent: May 7, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
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Patent number: 8435822Abstract: A method for forming a thin film photovoltaic device having patterned electrode films includes providing a soda lime glass substrate with an overlying lower electrode layer comprising a molybdenum material. The method further includes subjecting the lower electrode layer with one or more pulses of electromagnetic radiation from a laser source to ablate one or more patterns associated with one or more berm structures from the lower electrode layer. Furthermore, the method includes processing the lower electrode layer comprising the one or more patterns using a mechanical brush device to remove the one or more berm structures followed by treating the lower electrode layer comprising the one or more patterns free from the one or more berm structures. The method further includes forming a layer of photovoltaic material overlying the lower electrode layer and forming a first zinc oxide layer overlying the layer of photovoltaic material.Type: GrantFiled: December 7, 2010Date of Patent: May 7, 2013Assignee: Stion CorporationInventor: Robert D. Wieting
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Patent number: 8426321Abstract: A process for making a dielectric material where a precursor polymer selected from poly(phenylene vinylene)polyacetylene, poly(p-phenylene), poly(thienylene vinylene), poly(1,4-naphthylene vinylene), and poly(p-pyridine vinylene) is energized said by exposure by radiation or increase in temperature to a level sufficient to eliminate said leaving groups contained within the precursor polymer, thereby transforming the dielectric material into a conductive polymer. The leaving group in the precursor polymer can be a chloride, a bromide, an iodide, a fluoride, an ester, an xanthate, a nitrile, an amine, a nitro group, a carbonate, a dithiocarbamate, a sulfonium group, an oxonium group, an iodonium group, a pyridinium group, an ammonium group, a borate group, a borane group, a sulphinyl group, or a sulfonyl group.Type: GrantFiled: May 2, 2011Date of Patent: April 23, 2013Assignee: Sandia CorporationInventors: Shawn M. Dirk, Ross S. Johnson, David R. Wheeler, Gregory R. Bogart
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Patent number: 8415728Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: November 12, 2010Date of Patent: April 9, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8409982Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and seconType: GrantFiled: July 14, 2011Date of Patent: April 2, 2013Assignee: PPG Industries Ohio, Inc.Inventors: Kevin C. Olson, Alan E. Wang
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Patent number: 8394665Abstract: A method of manufacturing an organic thin film transistor, the method comprising: depositing a source and drain electrode; forming a thin self-assembled layer of material on the source and drain electrodes, the thin self-assembled layer of material comprising a dopant moiety for chemically doping an organic semi-conductive material by accepting or donating charge and a separate attachment moiety bonded to the dopant moiety and selectively bonded to the source and drain electrodes; and depositing a solution comprising a solvent and an organic semi-conductive material in a channel region between the source and drain electrode.Type: GrantFiled: June 13, 2008Date of Patent: March 12, 2013Assignees: Cambridge Display Technology Limited, Panasonic CorporationInventors: Sadayoshi Hotta, Jonathan Halls, Gregory Whiting
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Patent number: 8354349Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.Type: GrantFiled: March 19, 2010Date of Patent: January 15, 2013Assignee: Casio Computer Co., Ltd.Inventor: Junji Shiota
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Patent number: 8293570Abstract: A light emitting device includes a substrate and a plurality of pixel rows. The pixel rows are arranged on the substrate. Each of the pixel rows includes a first sub-pixel row having a plurality of first sub-pixels, a second sub-pixel row having a plurality of second sub-pixels, and a third sub-pixel row having a plurality of third sub-pixels. In the mth pixel row, each first sub-pixel includes a first structure layer, the first structure layers are separated from each other and each corresponds to one first sub-pixel. In the (m+n)th pixel row, the first sub-pixels include a first common structure layer, the first common structure layer corresponds to a plurality of first sub-pixels in a same row. The first structure layer and the first common structure layer commonly act as an organic functional layer or an electrode layer, and m, n are each a positive integer.Type: GrantFiled: March 29, 2012Date of Patent: October 23, 2012Assignee: Au Optronics CorporationInventors: Yuan-Ming Chiang, Wen-Hao Wu
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Patent number: 8288767Abstract: A method for forming a thin-film transistor (TFT) includes providing a substrate, forming a first patterned conducting layer on the substrate, forming an organic dielectric layer on the first patterned conducting layer and the substrate, forming a seeding layer on the organic dielectric layer, using the seeding layer as a crystal growing base to form an inorganic semiconductor layer on the seeding layer, and forming a second patterned conducting layer on the inorganic semiconductor layer.Type: GrantFiled: January 4, 2010Date of Patent: October 16, 2012Assignee: National Taiwan UniversityInventors: Ching-Fuh Lin, Chun-Yu Lee
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Patent number: 8283205Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.Type: GrantFiled: January 13, 2012Date of Patent: October 9, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
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Patent number: 8269317Abstract: Compounds comprising a ligand having a quinoline or isoquinoline moiety and a phenyl moiety, e.g., (iso)pq ligands. In particular, the ligand is further substituted with electron donating groups. The compounds may be used in organic light emitting devices, particularly devices with emission in the deep red part of the visible spectrum, to provide devices having improved properties.Type: GrantFiled: November 11, 2010Date of Patent: September 18, 2012Assignee: Universal Display CorporationInventors: Bert Alleyne, Raymond Kwong
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Publication number: 20120228576Abstract: A storage device includes: a plurality of first electrode wirings; a plurality of second electrode wirings which cross the first electrode wirings; a via plug which is formed between the second electrode wiring and the two adjacent first electrode wirings, and in which a maximum diameter of a bottom surface opposing the first electrode wirings in a direction vertical to a direction in which the first electrode wirings stretch is smaller than a length corresponding to a pitch of the first electrode wiring plus a width of the first electrode wirings; a first storage element which is formed between the via plug and one of the two first electrode wirings; and a second storage element which is formed between the via plug and the other one of the two first electrode wirings.Type: ApplicationFiled: September 20, 2011Publication date: September 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji Asakawa, Shigeki Hattori, Hideyuki Nishizawa, Satoshi Mikoshiba, Reika Ichihara, Masaya Terai
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Patent number: 8258065Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.Type: GrantFiled: October 19, 2009Date of Patent: September 4, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Bomy Chen, Long Ching Wang, Sychyi Fang
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Patent number: 8222705Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.Type: GrantFiled: May 7, 2010Date of Patent: July 17, 2012Assignee: Sony CorporationInventors: Akiko Ogino, Yukihiro Sayama, Takayuki Shoya, Masaya Shimoji
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Patent number: 8202759Abstract: The present invention provides a manufacturing method of an organic semiconductor device comprising a step of transferring an organic semiconductor layer to a gate insulation layer by a thermal transfer at a liquid crystal phase transition temperature of a liquid crystalline organic semiconductor material, and the step uses: an organic semiconductor layer-transferring substrate comprising a parting substrate having parting properties, and the organic semiconductor layer formed on the parting substrate and containing the liquid crystalline organic semiconductor material; and a substrate for forming an organic semiconductor device comprising a substrate, a gate electrode formed on the substrate, and the gate insulation layer formed to cover the gate electrode and having alignment properties which are capable of aligning the liquid crystalline organic semiconductor material on a surface of the gate insulation layer.Type: GrantFiled: January 21, 2009Date of Patent: June 19, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Ken Tomino, Masanao Matsuoka, Tomomi Suzuki, Hiroki Maeda
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Patent number: 8198715Abstract: A MEMS transducer includes a substrate, a membrane layer and a back-plate layer. The membrane layer is supported by the substrate. The back-plate layer is supported by the membrane layer and includes a respective sidewall portion and a respective raised portion. One or more columns, separate from the sidewall portion of the back-plate layer, connect the back-plate layer, the membrane layer and the substrate.Type: GrantFiled: September 18, 2008Date of Patent: June 12, 2012Assignee: Wolfson Microelectronics plcInventors: Richard Ian Laming, Colin Robert Jenkins
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Patent number: 8198128Abstract: The invention provides a method for fabricating a nano-array comprising the following steps. A template with a plurality of nano-holes is provided. A polymer is embossed by the template to integrally form a plurality of nano-protrusions thereon, and demolding to reveal the nano-protrusions. The nano-protrusion has a concave or convex top surface.Type: GrantFiled: December 1, 2009Date of Patent: June 12, 2012Assignee: Industrial Technology Research InstituteInventors: Chih-Chiang Chao, Po-Ling Shiao, Mei-Chun Lai
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Patent number: 8133768Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: September 15, 2009Date of Patent: March 13, 2012Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the Unites States National Aeronautics and Space AdministrationInventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8114468Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.Type: GrantFiled: June 18, 2008Date of Patent: February 14, 2012Assignee: Boise Technology, Inc.Inventors: Gurtej Sandhu, John Smythe, Bhaskar Srinivasan
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Patent number: 8105872Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.Type: GrantFiled: June 2, 2010Date of Patent: January 31, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Yaojian Lin
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Patent number: 8101857Abstract: An organic device, including an organic compound having charge-transporting ability (i.e., transporting holes and/or electrons) and/or including organic light emissive molecules capable of emitting at least one of fluorescent light or phosphorescent light, has a charge transfer complex-contained layer including a charge transfer complex formed upon contact of an organic hole-transporting compound and molybdenum trioxide via a manner of lamination or mixing thereof, so that the organic hole-transporting compound is in a state of radical cation (i.e., positively charged species) in the charge transfer complex-contained layer.Type: GrantFiled: July 7, 2005Date of Patent: January 24, 2012Assignees: ROHM Co., Ltd., Mitsubishi Heavy Industries, Ltd.Inventors: Junji Kido, Toshio Matsumoto, Takeshi Nakada
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Patent number: 8101530Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.Type: GrantFiled: September 25, 2009Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Hsiung Huang, Chin-Hsiang Lin, Heng-Jen Lee, Heng-Hsin Liu
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Patent number: 8097490Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.Type: GrantFiled: August 27, 2010Date of Patent: January 17, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
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Patent number: 8053376Abstract: In a method of making a polymer structure on a substrate a layer of a first polymer, having a horizontal top surface, is applied to a surface of the substrate. An area of the top surface of the polymer is manipulated to create an uneven feature that is plasma etched to remove a first portion from the layer of the first polymer thereby leaving the polymer structure extending therefrom. A light emitting structure includes a conductive substrate from which an elongated nanostructure of a first polymer extends. A second polymer coating is disposed about the nanostructure and includes a second polymer, which includes a material such that a band gap exists between the second polymer coating and the elongated nanostructure. A conductive material coats the second polymer coating. The light emitting structure emits light when a voltage is applied between the conductive substrate and the conductive coating.Type: GrantFiled: June 26, 2009Date of Patent: November 8, 2011Assignee: Georgia Tech Research CorporationInventors: Zhong L. Wang, Xudong Wang, Jenny R. Morber, Jin Liu
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Patent number: 8044389Abstract: A method of producing an electronic or electro-optic device, and the devices produced, includes producing a first electrode by a solution process, producing a second electrode by a solution process, and lamination an active polymer layer between the first and second electrodes.Type: GrantFiled: July 28, 2008Date of Patent: October 25, 2011Assignee: The Regents of the University of CaliforniaInventors: Yang Yang, Jinsong Huang
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Patent number: 8030139Abstract: A method of producing a thin film transistor includes a gate electrode formation step that forms a gate electrode on a substrate, a gate insulating layer formation step that forms a gate insulating layer on the substrate in such a manner as to cover the gate electrode formed in the gate electrode formation step, a source/drain electrodes formation step that forms a source electrode and a drain electrode on the gate insulating layer, and a semiconductor layer formation step that applies an aqueous solution for semiconductor layer formation which is an aqueous solution comprising at least a single wall carbon nanotube and a surfactant between the source electrode and the drain electrode formed in the source/drain electrodes formation step by a coating process to form a semiconductor layer comprising the single wall carbon nanotube.Type: GrantFiled: March 25, 2009Date of Patent: October 4, 2011Assignee: Brother Kogyo Kabushiki KaishaInventors: Takeshi Asano, Taishi Takenobu, Masashi Shiraishi
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Patent number: 8030200Abstract: A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.Type: GrantFiled: September 23, 2009Date of Patent: October 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-Cheol Bae, Jong-Hyun Lee, Jong Tae Moon
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Patent number: 8017431Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of: (1) coating a solution containing an organic semiconductor material on a water-repellent surface of a water-repellent stamp substrate; (2) drying the thus coated organic semiconductor material-containing solution on the water-repellent surface to crystallize the organic semiconductor material in contact with the water-repellent surface, thereby forming a semiconductor layer; (3) thermally treating the semiconductor layer formed on the stamp substrate; and (4) pressing the stamp substrate at a side, in which the thermally treated organic semiconductor layer is formed, against a surface of a substrate to be transferred so that the organic semiconductor layer is transferred to the surface of the substrate to be transferred.Type: GrantFiled: January 5, 2007Date of Patent: September 13, 2011Assignee: Sony CorporationInventor: Akhiro Nomoto
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Patent number: 8008188Abstract: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.Type: GrantFiled: June 11, 2007Date of Patent: August 30, 2011Assignee: PPG Industries Ohio, Inc.Inventors: Kevin C. Olson, Alan E. Wang
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Patent number: 7999362Abstract: A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device.Type: GrantFiled: January 25, 2008Date of Patent: August 16, 2011Assignee: Infineon Technologies AGInventors: Hannes Mio, Horst Groeninger, Hermann Vilsmeier
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Patent number: 7981812Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.Type: GrantFiled: July 3, 2008Date of Patent: July 19, 2011Assignee: Applied Materials, Inc.Inventors: Kang-Lie Chiang, Chia-Ling Kao
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Patent number: 7981814Abstract: A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices.Type: GrantFiled: August 31, 2007Date of Patent: July 19, 2011Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventor: Charles Daniel Schaper
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Patent number: 7972885Abstract: This invention relates to imaging device and its related transferring technologies to independent substrate able to attain significant broadband capability covering the wavelengths from ultra-violet (UV) to long-Infrared. More particularly, this invention is related to the broadband image sensor (along with its manufacturing technologies), which can detect the light wavelengths ranges from as low as UV to the wavelengths as high as 20 ?m covering the most of the wavelengths using of the single monolithic image sensor on the single wafer. This invention is also related to the integrated circuit and the bonding technologies of the image sensor to standard integrated circuit for multicolor imaging, sensing, and advanced communication. Our innovative approach utilizes surface structure having more than micro-nano-scaled 3-dimensional (3-D) blocks which can provide broad spectral response.Type: GrantFiled: September 24, 2009Date of Patent: July 5, 2011Assignee: Banpil Photonics, Inc.Inventors: Achyut Kumar Dutta, Robert Allen Olah