Schottky Electrode (epo) Patents (Class 257/E21.047)
  • Patent number: 10643993
    Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 5, 2020
    Assignee: Win Semiconductors Corp.
    Inventors: Hsi-Tsung Lin, Yan-Cheng Lin, Sheng-Hsien Liu
  • Patent number: 10153276
    Abstract: In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a Group III nitride based semiconductor device arranged on the silicon carbide layer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Khalil Hosseini, Frank Kahlmann
  • Patent number: 8987753
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8962461
    Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
  • Patent number: 8896086
    Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit Arora, Prashant Bhargava, Rishi Bhooshan
  • Patent number: 8865543
    Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhiqiang Li, Xia An, Yue Guo, Xing Zhang
  • Patent number: 8618615
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 31, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Se hyun Kim
  • Patent number: 8486816
    Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8476154
    Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: July 2, 2013
    Assignee: Fudan University
    Inventors: Dongping Wu, Shi-Li Zhang
  • Patent number: 8476646
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 2, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8183103
    Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 22, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Yan-Hsiu Liu
  • Publication number: 20120086099
    Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
  • Patent number: 7989277
    Abstract: A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: August 2, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Louis Luh, Keh-Chung Wang, Wah S. Wong, Miroslav Micovic, David Chow, Don Hitko
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Patent number: 7851831
    Abstract: A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. A first portion of the gate electrode layer, in contact with the nitride semiconductor layer, has a higher nitrogen mole fraction than a second portion of the gate electrode layer.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Koyama, Yoshitaka Kamo, Toshihiko Shiga
  • Patent number: 7829448
    Abstract: Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMIC); and a method of producing the same. The MOS-PHEMT structure is characterized in having a gate dielectric layer formed by atomic deposition from a gate dielectric selected from the group consisting of Al2O3, HfO2, La2O3, and ZrO2, and thereby rendering the semiconductor structure comprising the same, such as a high frequency switch device, to have less DC power loss, less insertion loss and better isolation.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 9, 2010
    Assignee: National Chiao Tung University
    Inventors: Edward Yi. Chang, Yun-Chi Wu, Yueh-Chin Lin
  • Patent number: 7816240
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 19, 2010
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Patent number: 7777292
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20100117098
    Abstract: To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode. A Schottky electrode which includes: scattered island-form pattern Pt-group alloy thin films which are formed on a diamond surface formed on a substrate, in which the Pt-group alloy includes 50 to 99.9 mass % of Pt and 0.
    Type: Application
    Filed: April 14, 2008
    Publication date: May 13, 2010
    Inventors: Kazuhiro Ikeda, Hitoshi Umezawa, Shinichi Shikata
  • Patent number: 7709269
    Abstract: Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: May 4, 2010
    Assignee: Cree, Inc.
    Inventors: Richard Peter Smith, Scott T. Sheppard
  • Patent number: 7671383
    Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: March 2, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7649237
    Abstract: A semiconductor diode that eliminates leakage current and reduces parasitic resistance is disclosed. The semiconductor diode comprises a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate, wherein the semiconductor layer includes a first dopant and a first well with a Schottky region; and a polysilicon device positioned above the semiconductor layer and adjacent to the first well with the Schottky region.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: January 19, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shou-Mao Chen
  • Patent number: 7645691
    Abstract: A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 12, 2010
    Assignee: Micrel, Inc.
    Inventor: Schyi-yi Wu
  • Patent number: 7507650
    Abstract: A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide epitaxial layer, wherein a Schottky electrode made of molybdenum, tungsten, or an alloy thereof is formed on the surface of the silicon carbide epitaxial layer and is subjected to heat treatment so as to induce an alloying reaction at an interface of the silicon carbide epitaxial layer and the Schottky electrode, thereby forming an alloy layer at the interface, whereby the height of a Schottky barrier is controlled while maintaining an n-factor at a nearly constant low value.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: March 24, 2009
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
  • Patent number: 7449728
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 11, 2008
    Assignee: Tri Quint Semiconductor, Inc.
    Inventor: Walter Anthony Wohlmuth
  • Patent number: 7417271
    Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Stefanovich Genrikh, Choong-rae Cho, In-kyeong Yoo, Eun-hong Lee, Sung-Il Cho, Chang-wook Moon
  • Patent number: 7411218
    Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 12, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: William F. Seng, Richard L. Woodin, Carl Anthony Witt
  • Patent number: 7407859
    Abstract: A compound semiconductor device has: a substrate; a GaN channel layer; an n-type AlqGal-qN (0<q (1) electron supply layer; an n-type GaN cap layer; a gate electrode disposed on the cap layer and forming a Schottky contact; recesses formed on both sides of the gate electrode on source and drain sides by at least partially removing the cap layer, the recesses having a bottom surface of a roughness larger than a roughness of a surface of the cap layer under the gate electrode; a source electrode disposed on the bottom surface of the recess on the source side; and a drain electrode disposed on the bottom surface of the recess on the drain side.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 5, 2008
    Assignee: Fujitsu Limited
    Inventors: Tokuharu Kimura, Toshihide Kikkawa
  • Patent number: 7371668
    Abstract: A method for making a MOS device includes: forming an insulator layer on a semiconductor substrate, the insulator layer including a titanium dioxide film that has a surface with hydroxyl groups formed thereon; and forming an aluminum cap film on the surface of the titanium dioxide film, and conducting annealing operation of the aluminum cap film at an annealing temperature sufficient to permit formation of active hydrogen atoms through reaction of the aluminum cap film and the hydroxyl groups, thereby enabling hydrogen passivation of oxide traps in the titanium dioxide film through diffusion of the active hydrogen atoms into the titanium dioxide film.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: May 13, 2008
    Assignee: National Sun Yat-Sen University
    Inventors: Ming-Kwei Lee, Jung-Jie Huang, Yu-Hsiang Hung
  • Patent number: 7368371
    Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n? silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 6, 2008
    Assignee: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 7268027
    Abstract: Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrier layer, and the cap layer with the exception of a region corresponding to HEMT and MSM PD; forming a source electrode and a drain electrode of HEMT; removing the cap layer from a region corresponding to a gate electrode of HEMT and a Schottky electrode of MSM PD; forming the gate electrode of HEMT and the Schottky electrode of HEMT on the cap layer-removed region; and removing the cap layer, the barrier layer and the channel layer from a region corresponding to an optical waveguide, to expose the optical waveguide.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: September 11, 2007
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Young Se Kwon, Jung Ho Cha
  • Patent number: 7250666
    Abstract: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: July 31, 2007
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Nowak
  • Publication number: 20070134897
    Abstract: A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide epitaxial layer, wherein a Schottky electrode made of molybdenum, tungsten, or an alloy thereof is formed on the surface of the silicon carbide epitaxial layer and is subjected to heat treatment so as to induce an alloying reaction at an interface of the silicon carbide epitaxial layer and the Schottky electrode, thereby forming an alloy layer at the interface, whereby the height of a Schottky barrier is controlled while maintaining an n-factor at a nearly constant low value.
    Type: Application
    Filed: March 25, 2005
    Publication date: June 14, 2007
    Applicant: Central Research Institite of Electric Power Industry
    Inventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
  • Patent number: 7186625
    Abstract: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Louis L. Hsu, Joseph F. Shepard, Jr., William R. Tonti