Abstract: Methods for forming Cu—In—Ga—N (CIGN) layers for use in TFPV solar panels are described using reactive PVD deposition in a nitrogen containing atmosphere. In some embodiments, the CIGN layers can be used as an absorber layer and eliminate the need of a selenization step. In some embodiments, the CIGN layers can be used as a protective layer to decrease the sensitivity of the CIG layer to oxygen or moisture before the selenization step. In some embodiments, the CIGN layers can be used as an adhesion layer to improve the adhesion between the back contact layer and the absorber layer.

Abstract: Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H2O2 and HNO3 to remove damaged chalcogenide from the sidewalls of the memory cell structures.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract: The method and system for selenization in fabricating CIS and/or CIGS based thin film solar cell overlaying cylindrical glass substrates. The method includes providing a substrate, forming an electrode layer over the substrate and depositing a precursor layer of copper, indium, and/or gallium over the electrode layer. The method also includes disposing the substrate vertically in a furnace. Then a gas including a hydrogen species, a selenium species and a carrier gas are introduced into the furnace and heated to between about 350° C. and about 450° C. to at least initiate formation of a copper indium diselenide film from the precursor layer.

Abstract: A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed.

Abstract: An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices.

Abstract: Provision of a solid-state imaging device of a planarized structure with reduced dark currents, allowing for high sensitivities over a wide wavelength band ranging from visible wavelengths to near-infrared wavelengths, and a fabrication method of the same.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.

Abstract: A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.

Abstract: Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack.

Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Abstract: A phase change material comprises GexSbyTez, wherein a Ge atomic concentration x is within a range from 30% to 65%, a Sb atomic concentration y is within a range from 13% to 27% and a Te atomic concentration z is within a range from 20% to 45%. A Ge-rich family of such materials is also described. A memory device, suitable for integrated circuits, comprising such materials is described.

Abstract: A method for deposition of a selenium thin-film includes the following steps. First, a plasma head is provided. Then, a substrate is supported in an atmospheric pressure. Next, a solid-state selenium source is dissociated by the plasma head to deposit the selenium thin-film on the substrate. The plasma head includes a chamber, a housing and the solid-state selenium source. Plasma is produced in the chamber. The chamber is surrounded by the housing. The solid-state selenium source is supported by the housing.

Abstract: A process of producing a resistivity-change memory cell is described. The process includes a deposition at room temperature, in amorphous state, of a layer of a nitrogen (N)-doped alloy of germanium (Ge) and tellurium (Te) to constitute the resistivity-change material of the memory cell. An annealing is then performed such as to limit the type of re-crystallisation by nucleation starting from the amorphous state of the phase-change material. The material used and the process permit the data retention at high temperature to be significantly improved.

Abstract: A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Abstract: A selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.

Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Abstract: Methods for forming Cu—In—Ga—N (CIGN) layers for use in TFPV solar panels are described using reactive PVD deposition in a nitrogen containing atmosphere. In some embodiments, the CIGN layers can be used as an absorber layer and eliminate the need of a selenization step. In some embodiments, the CIGN layers can be used as a protective layer to decrease the sensitivity of the CIG layer to oxygen or moisture before the selenization step. In some embodiments, the CIGN layers can be used as an adhesion layer to improve the adhesion between the back contact layer and the absorber layer.

Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.

Abstract: There is provide a substrate processing apparatus, comprising: a processing chamber configured to house a plurality of substrates with a laminated film formed thereon which is composed of any one of copper-indium, copper-gallium, or copper-indium-gallium; a gas supply tube configured to introduce elemental selenium-containing gas or elemental sulfur-containing gas into the processing chamber; an exhaust tube configured to exhaust an atmosphere in the processing chamber; and a heating section provided so as to surround the reaction tube, wherein a base of the reaction tube is made of a metal material.

Abstract: A selenium/Group Ib/Group 3a ink is provided, comprising, as initial components: (a) a selenium/Group Ib/Group 3a system which comprises a combination of, as initial components: a selenium; an organic chalcogenide component; a Group Ib containing substance; optionally, a bidentate thiol component; a Group 3a containing substance; and, (b) a liquid carrier component; wherein the selenium/Group Ib/Group 3a system is stably dispersed in the liquid carrier component. Also provided are methods of preparing the selenium/Group Ib/Group 3a ink and for using the selenium/Group Ib/Group 3a ink to deposit a selenium/Group Ib/Group 3a material on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photoresponsive devices (e.g., electrophotography (e.g.

Abstract: A selenium ink comprising selenium stably dispersed in a liquid medium is provided, wherein the selenium ink is hydrazine free and hydrazinium free. Also provided are methods of preparing the selenium ink and of using the selenium ink to deposit selenium on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photo responsive devices (e.g., electrophotography (e.g., laser printers and copiers), rectifiers, photographic exposure meters and photo voltaic cells) and chalcogenide containing phase change memory materials.

Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.

Abstract: A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR)3 to a substrate, where R is alkyl, and forming there-from antimony-comprising phase change material on the substrate. The phase change material has no greater than 10 atomic percent oxygen, and includes another metal in addition to antimony.

Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.

Abstract: Systems and processes for treatment of a cadmium telluride thin film photovoltaic device are generally provided. The systems can include a treatment system and a conveyor system. The treatment system includes a preheating section, a treatment chamber, and an anneal oven that are integrally interconnected within the treatment system. The conveyor system is operably disposed within the treatment system and configured for transporting substrates in a serial arrangement into and through the preheat section, into and through the treatment chamber, and into and through the anneal oven at a controlled speed. The treatment chamber is configured for applying a material to a thin film on a surface of the substrate and the anneal oven is configured to heat the substrate to an annealing temperature as the substrates are continuously conveyed by the conveyor system through the treatment chamber.

Abstract: A system is provided for heating or cooling discrete, linearly conveyed substrates having a gap between a trailing edge of a first substrate and a leading edge of a following substrate in a conveyance direction. The system includes a chamber, and a conveyor operably configured within the chamber to move the substrates through at a conveyance rate. A plurality of individually controlled temperature control units, for example heating or cooling units, are disposed linearly within the chamber along the conveyance direction. A controller is in communication with the temperature control units and is configured to cycle output of the temperature control units from a steady-state temperature output as a function of the spatial position of the conveyed substrates within the chamber relative to the temperature control units so as to decrease temperature variances in the substrates caused by movement of the substrates through the chamber.

Abstract: Some embodiments include methods of forming metal-containing structures. A first metal-containing material may be formed over a substrate. After the first metal-containing material is formed, and while the substrate is within a reaction chamber, hydrogen-containing reactant may be used to form a hydrogen-containing layer over the first metal-containing material. The hydrogen-containing reactant may be, for example, formic acid and/or formaldehyde. Any unreacted hydrogen-containing reactant may be purged from within the reaction chamber, and then metal-containing precursor may be flowed into the reaction chamber. The hydrogen-containing layer may be used during conversion of the metal-containing precursor into a second metal-containing material that forms directly against the first metal-containing material. Some embodiments include methods of forming germanium-containing structures, such as, for example, methods of forming phase change materials containing germanium, antimony and tellurium.

Abstract: During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation.

Abstract: A method of forming a material comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.

Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.

Abstract: Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate.

Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.

Abstract: Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (?) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

Abstract: A thermal evaporation apparatus for depositing of a material on a substrate is described. The apparatus can comprise material storage means; heating means to generate a vapour of the material in the material storage means; vapour outlet means comprising a vapour receiving pipe having vapour outlet passages, and emission reducing means arranged such that an external surface of the vapour outlet means directed to said substrate exhibits low emission. Also the use of the apparatus, and a method of depositing a material onto a substrate by thermal evaporation are described.

Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

Abstract: A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal.

Abstract: A film-forming method includes a preprocessing step (step 1) wherein the inside of a processing chamber is exposed to a gas containing Cl and/or F in a state having no substrate in the processing chamber, and a step (step 2) wherein a substrate is loaded into the processing chamber after the step 1. Then, in a step 3, a gaseous Ge raw material, a gaseous Sb raw material, and a gaseous Te raw material are introduced into the processing chamber having the substrate loaded therein, and a Ge—Sb—Te film formed of Ge2Sb2Te5 is formed on the substrate by CVD.

Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.

Abstract: A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.