Epitaxial Deposition Of Group Iv Element, E.g., Si, Ge (epo) Patents (Class 257/E21.092)
  • Patent number: 10074734
    Abstract: Semiconductor structure including germanium-on-insulator lateral bipolar junction transistors and methods of fabricating the same generally include formation of a silicon passivation layer at an interface between the insulator layer and a germanium layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 10032897
    Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 8999805
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: October 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8946064
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
  • Patent number: 8937366
    Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 20, 2015
    Assignee: STC.UNM
    Inventors: Sang M. Han, Darin Leonhardt, Swapnadip Ghosh
  • Patent number: 8937343
    Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Hoi Sung Chung, Naein Lee
  • Patent number: 8928126
    Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8859402
    Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, patterning the epitaxial growth surface; placing a graphene layer on the patterned epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the patterned epitaxial growth surface. The epitaxial layer is grown from the exposed part of the patterned epitaxial growth surface and through the aperture.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: October 14, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8846464
    Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
  • Patent number: 8835995
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 8815712
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8785330
    Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Philippe Robert, Sophie Giroud
  • Patent number: 8709957
    Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ibrahim Alhomoudi
  • Patent number: 8703586
    Abstract: In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 22, 2014
    Assignee: KYOCERA Corporation
    Inventors: Norikazu Ito, Shinichiro Inaba, Hiroshi Matsui, Koichiro Niira
  • Patent number: 8685845
    Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
  • Patent number: 8664069
    Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8647929
    Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 11, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jin-Ping Han
  • Patent number: 8604529
    Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 10, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Han-Seob Cha
  • Patent number: 8524559
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8481357
    Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 9, 2013
    Assignee: Crystal Solar Incorporated
    Inventors: Ananda H. Kumar, Tirunelveli S. Ravi, Vidyut Gopal
  • Patent number: 8471321
    Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
  • Patent number: 8361869
    Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 29, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huajie Zhou, Yi Song, Qiuxia Xu
  • Patent number: 8350270
    Abstract: A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: January 8, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shoyu Watanabe, Shuhei Nakata, Kenichi Ohtsuka
  • Patent number: 8334214
    Abstract: A susceptor treatment method including placing a first substrate on a susceptor and forming a Si film on the first substrate by epitaxial growth, placing a second substrate on the susceptor in place of the first substrate and forming a SiC film on the second substrate by epitaxial growth, and allowing HCl gas to flow downward from above the susceptor while the susceptor, from which the second substrate has been removed, is heated to a temperature and rotated to remove the remaining crystalline grains derived from the epitaxial growth of Si film and the SiC film on the susceptor.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 18, 2012
    Assignees: NuFlare Technology, Inc., Denso Corporation
    Inventors: Kunihiko Suzuki, Shinichi Mitani
  • Patent number: 8314015
    Abstract: A process of silicon (Si) surface modification is provided for the electrochemical synthesis of Si particles in suspension. The process begins with a Si first substrate with a surface, and forms Si particles attached to the surface. Hydrogen-terminated Si particles are created and the first substrate is immersed in a hexane/1-octene (1/1 volume ratio) solution with a catalytic amount of chloroplatinic acid (H2PtCl6). 1-octene is bonded with the hydrogen-terminated Si particles, creating modified Si particles, with octane capping ligands, attached to the substrate surface. The first substrate is then exposed to ultrasonication, separating the modified Si particles from the first substrate. After removing the first substrate, a suspension is created of modified Si particles suspended in excess hexane/1-octene.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 20, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Chang-Ching Tu, Liang Tang, Apostolos T. Voutsas
  • Patent number: 8309986
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8293623
    Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 23, 2012
    Assignees: Showa Denko K.K., National Institute of Advanced Industrial Science and Technology, Central Research Institute of Electric Power Industry
    Inventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
  • Publication number: 20120228638
    Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 13, 2012
    Inventors: Mrinal K. Das, Michael Laughner
  • Publication number: 20120220109
    Abstract: A plasma CVD device comprises a vacuum vessel that houses a discharge electrode plate and a ground electrode plate to which is attached a substrate for thin film formation. The plasma CVD device has an earth cover at an interval from and facing the aforementioned discharge electrode plate; the aforementioned discharge electrode plate has gas inlets and exhaust outlets (which expel gas introduced through said gas inlets) that are connected at one end to equipment supplying raw gas for thin film formation and that open at the other end at the bottom face of the aforementioned discharge electrode plate; the aforementioned earth cover has second gas inlets corresponding to the aforementioned gas inlets, and second exhaust outlets corresponding to the aforementioned exhaust outlets. The plasma CVD device has an electric potential control plate disposed at an interval from and facing the aforementioned ground cover.
    Type: Application
    Filed: October 21, 2010
    Publication date: August 30, 2012
    Inventors: Tsunenori Komori, Takao Amioka, Keitaro Sakamoto
  • Publication number: 20120171849
    Abstract: In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode.
    Type: Application
    Filed: September 24, 2010
    Publication date: July 5, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Norikazu Ito, Shinichiro Inaba, Hiroshi Matsui, Koichiro Niira
  • Patent number: 8193592
    Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: June 5, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
  • Patent number: 8154050
    Abstract: A semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions includes an element formation region formed in the major surface of a semiconductor substrate, a gate electrode formed on a part of the element formation region, the semiconductor epitaxial layers formed in the source/drain regions of the element formation region so as to sandwich the channel region below the gate electrode, and silicide layers formed on the gate electrode and semiconductor epitaxial layers. Each semiconductor epitaxial layer has a three-layered structure in which first semiconductor films different in material or composition from the semiconductor substrate sandwich a second semiconductor film having a silicidation reactivity higher than that of the first semiconductor films. Each silicide layer extends to the second semiconductor film along the interface between the semiconductor substrate and semiconductor epitaxial layer.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8138070
    Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink containing a first set of nanoparticles and a first set of solvents, the first set of nanoparticles containing a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink containing a second set of nanoparticles and a second set of solvents, the second set of nanoparticles containing a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 20, 2012
    Assignee: Innovalight, Inc.
    Inventors: Maxim Kelman, Michael Burrows, Dmitry Poplavskyy, Giuseppe Scardera, Daniel Kray, Elena Rogojina
  • Publication number: 20120043556
    Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
  • Patent number: 8120060
    Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure also includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: February 21, 2012
    Assignee: Massachusetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Patent number: 8115195
    Abstract: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: February 14, 2012
    Assignee: Siltronic AG
    Inventors: Peter Storck, Martin Vorderwestner
  • Patent number: 8114755
    Abstract: A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: February 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yoshio Ozawa, Takashi Nakao, Akihito Yamamoto, Takashi Suzuki, Masahiro Kiyotoshi, Minako Inukai, Kaori Umezawa, Hiroaki Yamada
  • Patent number: 8076197
    Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 13, 2011
    Assignee: Intellectual Ventures II LLC
    Inventor: Han-Seob Cha
  • Patent number: 8071442
    Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: December 6, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Andreas Ott
  • Patent number: 8012860
    Abstract: A method for producing a product of a functionalized nanocomposition colloidal material using atomic layer deposition to coat the colloidal material. The ALD layer comprises an inorganic material which enables improved optical and electrical properties for the nanocomposite.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: September 6, 2011
    Assignee: UChicago Argonne, LLC
    Inventors: Jeffrey W. Elam, Philippe Guyot-Sionnest
  • Patent number: 7999250
    Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 16, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Bishnu Prasanna Gogoi, Robert Bruce Davies
  • Publication number: 20110189841
    Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.
    Type: Application
    Filed: April 11, 2011
    Publication date: August 4, 2011
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Min Zou, Li Cai, William David Brown
  • Patent number: 7977706
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: July 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 7960267
    Abstract: A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 14, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Konstantin V. Loiko, Brian A. Winstead, Taras A. Kirichenko
  • Patent number: 7960798
    Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Zhijiong Luo, Ricky S. Amos, Nivo Rovedo, Henry K. Utomo
  • Patent number: 7951685
    Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: May 31, 2011
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Hiroyuki Sazawa, Naohiro Nishikawa, Masahiko Hata
  • Publication number: 20110073909
    Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.
    Type: Application
    Filed: September 28, 2009
    Publication date: March 31, 2011
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Amlan Majumdar
  • Patent number: 7901968
    Abstract: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: March 8, 2011
    Assignee: ASM America, Inc.
    Inventors: Keith Doran Weeks, Paul D. Brabant