Deposition On Semiconductor Substrate Being Different From Deposited Semiconductor Material; I.e., Formation Of Heterojunctions (epo) Patents (Class 257/E21.093)
  • Patent number: 10482200
    Abstract: In one embodiment, the invention comprises: defining a first volume in a layer of a semiconductor device; calculating a probability of finding at least one dopant atom in the first volume, based on a dopant distribution of the layer; in the case that the calculated probability is equal to or greater than a pre-determined threshold, defining at least one additional volume in the layer substantially equal to the first volume; and in the case that the calculated probability is less than the pre-determined threshold: aggregating the first volume with a second volume adjacent the first volume, the second volume being substantially equal to the first volume; and recalculating a probability of finding at least one dopant atom in the aggregated first and second volumes, based on the dopant distribution of the layer.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Samarth Agarwal, Abhisek Dixit, Jeffrey B. Johnson
  • Patent number: 10103238
    Abstract: Methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial layers that are alternatingly arranged with the nanosheet channel layers. The body feature is located on a second sacrificial layer. The first sacrificial layers are recessed relative to the nanosheet channel layers to form a plurality of first cavities indented into a sidewall of the body feature. A plurality of dielectric spacers are formed that fill the first cavities. After forming the dielectric spacers, the second sacrificial layer is removed with an etching process to define a second cavity that extends completely beneath the body feature. A dielectric layer is formed in the second cavity.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Tek Po Rinus Lee, Haigou Huang, Ruilong Xie, Min Gyu Sung, Chanro Park
  • Patent number: 8937343
    Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Hoi Sung Chung, Naein Lee
  • Patent number: 8906758
    Abstract: The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: December 9, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Miguel E. Urteaga
  • Patent number: 8835995
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 8686396
    Abstract: An ultra-violet light-emitting device and method for fabricating an ultraviolet light emitting device, 12, (LED or an LD) with an AlInGaN multiple-quantum-well active region, 10, exhibiting stable cw-powers. The device includes a non c-plane template with an ultraviolet light-emitting structure thereon. The template includes a first buffer layer, 321, on a substrate, 100, then a second buffer layer, 421, on the first preferably with a strain-relieving layer, 302, in both buffer layers. Next there is a semiconductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600. Another semiconductor layer, 700, having a second type of conductivity is applied next. Two metal contacts, 980 and 990, are applied to this construction, one to the semiconductor layer having the first type of conductivity and the other to the semiconductor layer having the second type of conductivity, to complete the light emitting device.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: April 1, 2014
    Assignee: Nitek, Inc.
    Inventor: Asif Khan
  • Patent number: 8658451
    Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: February 25, 2014
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Patent number: 8629478
    Abstract: A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8507365
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a?) that is related to the substrate lattice parameter (a). The lattice parameter (a?) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 13, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak
  • Patent number: 8492245
    Abstract: Methods for making growth templates for the epitaxial growth of compound semiconductors and other materials are provided. The growth templates are thin layers of single-crystalline materials that are themselves grown epitaxially on a substrate that includes a thin layer of sacrificial material. The thin layer of sacrificial material, which creates a coherent strain in the single-crystalline material as it is grown thereon, includes one or more suspended sections and one or more supported sections.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 23, 2013
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, Deborah M. Paskiewicz, Boy Tanto
  • Patent number: 8460959
    Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: June 11, 2013
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Patent number: 8304756
    Abstract: An ultra-violet emitting light-emitting device and method for fabricating an ultraviolet light emitting device (LED) with an AlInGaN multiple-quantum-well active region exhibiting stable cw-powers. The LED includes a template with an ultraviolet light-emitting structure on it. The template includes a first buffer layer on a substrate, then a second buffer layer on the first preferably with a strain-relieving layer in both buffer layers. Next there is a semiconductor layer having a first type of conductivity followed by a layer providing a quantum-well region with an emission spectrum ranging from 190 nm to 369 nm. Another semiconductor layer having a second type of conductivity is applied next. Two metal contacts are applied to this construction, one to the semiconductor layer having the first type of conductivity and the other to the semiconductor layer having the second type of conductivity, to complete the LED.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 6, 2012
    Assignee: Nitek, Inc.
    Inventor: Asif Khan
  • Patent number: 8247261
    Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra Sadana
  • Patent number: 8211726
    Abstract: An object is to provide a method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf). The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor and an active layer formed between the n-type nitride semiconductor and the p-type nitride semiconductor, wherein the n-type nitride semiconductor includes at least an n-type contact layer and an n-side GaN layer, the n-side GaN layer consists of a single or a plurality of undoped and/or n-type layers, and the method includes the step of forming the n-side GaN layer by organic metal vapor deposition with the growth temperature set within the range of 500 to 1000° C., such that the n-side GaN layer is formed between the n-type contact layer and the active layer.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: July 3, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Komada, Mayuko Fudeta
  • Patent number: 8119428
    Abstract: An object is to provide a method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf). The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor and an active layer formed between the n-type nitride semiconductor and the p-type nitride semiconductor, wherein the n-type nitride semiconductor includes at least an n-type contact layer and an n-side GaN layer, the n-side GaN layer consists of a single or a plurality of undoped and/or n-type layers, and the method includes the step of forming the n-side GaN layer by organic metal vapor deposition with the growth temperature set within the range of 500 to 1000° C., such that the n-side GaN layer is formed between the n-type contact layer and the active layer.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 21, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Komada, Mayuko Fudeta
  • Publication number: 20120025195
    Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Kevin Andrew McComber, Jifeng Liu, Jurgen Michel, Lionel C. Kimerling
  • Patent number: 8093143
    Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 10, 2012
    Assignee: Siltronic AG
    Inventors: Peter Storck, Thomas Buschhardt
  • Patent number: 8017504
    Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Kai Frohberg
  • Patent number: 8012839
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jinping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 7989295
    Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 2, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7977134
    Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 12, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Hyuk Min Lee, Hyun Kyung Kim, Dong Joon Kim, Hyoun Soo Shin
  • Patent number: 7968363
    Abstract: A manufacture method for zinc oxide (ZnO) based semiconductor crystal includes providing a substrate having a Zn polarity plane; and reacting at least zinc (Zn) and oxygen (O) on the Zn polarity plane of said substrate to grow ZnO based semiconductor crystal on the Zn polarity plane of said substrate in a Zn rich condition. (a) An n-type ZnO buffer layer is formed on a Zn polarity plane of a substrate. (b) An n-type ZnO layer is formed on the surface of the n-type ZnO buffer layer. (c) An n-type ZnMgO layer is formed on the surface of the n-type ZnO layer. (d) A ZnO/ZnMgO quantum well layer is formed on the surface of the n-type ZnMgO layer, by alternately laminating a ZnO layer and a ZnMgO layer. @(e) A p-type ZnMgO layer is formed on the surface of the ZnO/ZnMgO quantum well layer. (f) A p-type ZnO layer is formed on the surface of the p-type ZnMgO layer. @(g) An electrode is formed on the n-type ZnO layer and p-type ZnO layer. The n-type ZnO layer is formed under a Zn rich condition at the step (b).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: June 28, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Hiroshi Kotani, Michihiro Sano, Hiroyuki Kato, Akio Ogawa
  • Patent number: 7910445
    Abstract: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Onoda
  • Patent number: 7902008
    Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Igor Peidous, Mario M. Pelella
  • Patent number: 7902025
    Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: March 8, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7883979
    Abstract: A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Zhong Tang Xuan, Shui-Ming Cheng, Sheng-Da Liu
  • Patent number: 7875535
    Abstract: A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: January 25, 2011
    Assignee: Fujitsu Limited
    Inventors: Toshihide Kikkawa, Kenji Imanishi
  • Patent number: 7842532
    Abstract: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the side surfaces of the one or more convex portions of the first nitride semiconductor layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: November 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Takizawa, Jun Shimizu, Tetsuzo Ueda
  • Patent number: 7842973
    Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 30, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Patent number: 7842537
    Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Brian S. Doyle
  • Patent number: 7759229
    Abstract: A charge-free method of forming a nanostructure at low temperatures on a substrate. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of least one of oxygen and nitrogen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the beam have an average kinetic energy in a range from about 1 eV to about 5 eV.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 20, 2010
    Assignee: Los Alamos National Security, LLC
    Inventors: Mark Hoffbauer, Elshan Akhadov
  • Patent number: 7671383
    Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: March 2, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20090189185
    Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Applicant: ASM AMERICA, INC.
    Inventors: Chantal ARENA, Pierre TOMASINI, Nyles CODY, Matthias BAUER
  • Patent number: 7510904
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiqing Ouyang, Jeremy D. Schaub
  • Publication number: 20090020748
    Abstract: Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 22, 2009
    Applicant: THE OHIO STATE UNIVERSITY RESEARCH FOUNDATION
    Inventors: Niu JIN, Paul R. Berger, Phillip E. Thompson
  • Patent number: 7456034
    Abstract: A nitride semiconductor device comprises: a well layer of nitride semiconductor containing In and Ga; barrier layers of nitride semiconductor sandwiching the well layer, containing Al and Ga, and having a larger band gap energy than the well layer; and a thin film layer provided between the well layer and the barrier layer. The thin film layer is formed during lowering of the substrate temperature after formation of the barrier layer or during elevation of the substrate temperature after formation of the well layer.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventors: Norio Ikedo, Yasuyuki Fukushima, Masaaki Yuri
  • Patent number: 7393762
    Abstract: A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 1, 2008
    Assignee: Los Alamos National Secruity, LLC
    Inventors: Mark Hoffbauer, Alex Mueller
  • Patent number: 7391098
    Abstract: The present invention relates to a semiconductor substrate, a semiconductor device with high carrier mobility and a method of manufacturing the same. According to the present invention, there are provided a semiconductor substrate comprising a silicon substrate, a single crystal germanium layer formed on the silicon substrate, and a silicon layer formed on the single crystal germanium layer; a semiconductor device comprising a gate electrode formed on the semiconductor substrate, and junctions formed in the substrate at both sides of the gate electrode; and a method of manufacturing the semiconductor device. Therefore, carrier mobility of channels can be enhanced since the channels of semiconductor devices are placed within the germanium layer. Further, since the silicon layer is formed on the germanium layer, the reliable gate insulation film can be formed and a leakage current produced in a junction layer can also be reduced.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: June 24, 2008
    Assignee: Jusung Engineering Co., Ltd.
    Inventor: Chul Ju Hwang
  • Patent number: 7297589
    Abstract: A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the subcollector region including depositing a material composition transition from a relatively larger bandgap material nearer the substrate to a relatively smaller bandgap material adjacent the collector; and the step of depositing the collector region including depositing a material composition transition from a relatively smaller bandgap material adjacent the subcollector to a relatively larger bandgap material adjacent the base.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: November 20, 2007
    Assignee: The Board of Trustees of The University of Illinois
    Inventor: Milton Feng
  • Patent number: 7241647
    Abstract: A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: July 10, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Shawn G. Thomas, Ted R. White, Chun-Li Liu, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean
  • Patent number: 7229901
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally