Diffusion Of Impurity Material, E.g., Doping Material, Electrode Material, Into Or Out Of A Semiconductor Body, Or Between Semiconductor Regions; Interactions Between Two Or More Impurities; Redistribution Of Impurities (epo) Patents (Class 257/E21.135)
  • Publication number: 20140001547
    Abstract: A semiconductor device includes a doped layer which contains a first dopant of a first conductivity type. In the doped layer, a counter-doped zone is formed in an edge area that surrounds an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type, which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of a concentration of the first dopant. The dopants in the counter-doped zone decrease charge carrier mobility and minority carrier lifetime such that the dynamic robustness of the semiconductor device is increased.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
  • Publication number: 20130320462
    Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: VISHAY-SILICONIX
    Inventors: Naveen Tipirneni, Deva N. Pattanayak
  • Publication number: 20130320512
    Abstract: A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Peter Irsigler, Hans-Joachim Schulze
  • Patent number: 8592894
    Abstract: A method of forming a power semiconductor device comprises forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device; forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer; forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a junction between the body region and the epitaxial layer is at or substantially adjacent to a region of the epitaxial layer having a maximum doping concentration; and forming a gate region such that the gate region is adjacent at least a portion of the body region. In operation of the semiconductor device, the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Michel Reynes, Evgueniy Stafanov, Yann Weber
  • Patent number: 8575010
    Abstract: The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Alexis Drouin, Bernard Aspar, Christophe Desrumaux, Olivier Ledoux, Christophe Figuet
  • Patent number: 8569831
    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Lars P. Heineck, Shyam Surthi, Jaydip Guha
  • Patent number: 8569158
    Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8564099
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 22, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20130270572
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Applicant: HRL LABORATORIES, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Patent number: 8524559
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8513642
    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric
  • Patent number: 8513754
    Abstract: A solar cell includes a substrate of a first conductive type; an emitter layer that is positioned on the substrate and is a second conductive type that is opposite to the first conductive type; first electrodes that are connected to the emitter layer; and a second electrode that is connected to the substrate, wherein the emitter layer includes a first emitter portion and a second emitter portion, the first electrodes include a finger electrode, and a bus electrode intersecting and connected to the finger electrode, and the first emitter portion and the second emitter portion are positioned under the bus electrode.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 20, 2013
    Assignee: LG Electronics Inc.
    Inventor: JaeSung You
  • Patent number: 8508016
    Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 13, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Ulrich Schlapbach, Arnost Kopta
  • Publication number: 20130200443
    Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: International Business Machines Corporation
    Inventors: Christian Lavoie, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Paul Michael Solomon, Yanning Sun, Zhen Zhang
  • Patent number: 8501586
    Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 6, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Arnost Kopta, Stefan Linder
  • Patent number: 8497570
    Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
  • Patent number: 8497205
    Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Mitsuaki Izuha
  • Patent number: 8492272
    Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Alvin J. Joseph
  • Publication number: 20130183816
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method of manufacturing a semiconductor device, a first layer containing Si is formed on a semiconductor substrate. An impurity region and a non-impurity region are formed in the first layer by selectively diffusing an impurity into the first layer. A second layer containing a metal material is formed on the first layer. The metal material is diffused into the non-impurity region by annealing the second layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 18, 2013
    Inventor: Shuichi TANIGUCHI
  • Patent number: 8481381
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8475690
    Abstract: An embodiment of the present invention relates to a diffusing agent composition used in printing an impurity-diffusing component onto a semiconductor substrate, wherein the diffusing agent composition contains: a hydrolysis product of alkoxysilane (A); a component (B) containing at least one selected from the group consisting of a hydrolysis product of alkoxy titanium, a hydrolysis product of alkoxy zirconium, titania fine particle, and zirconia fine particle; an impurity-diffusing component (C); and an organic solvent (D).
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 2, 2013
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Takashi Kamizono, Toshiro Morita, Atsushi Murota, Motoki Takahashi, Katsuya Tanitsu, Takaaki Hirai
  • Publication number: 20130154109
    Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
  • Patent number: 8466035
    Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: June 18, 2013
    Assignee: Dynaloy, LLC
    Inventors: Kimberly Dona Pollard, Allison C. Tonk
  • Patent number: 8461032
    Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas Bateman, Atul Gupta, Christopher Hatem, Deepak Ramappa
  • Publication number: 20130140705
    Abstract: Aspects of the present invention are directed to circuits, circuit packages and related methods. In accordance with various example embodiments, respective electrodes are implemented to facilitate contact to a semiconductor device via different surfaces and/or sidewalls, as may be useful in connecting the device to an external package having a plurality of semiconductor devices in which same-surface connections to the devices are spatially restricted. The semiconductor device has opposing surfaces and sidewalls connecting the surfaces, and contacts to respective different regions in the device. Respective electrodes are coupled to the respective contacts and extend along/around the device to provide access to the contacts via different surfaces.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Roelf Anco Jacob Groenhuis, Sven Walczyk, Emiel Bruin, Rolf Brenner
  • Publication number: 20130140633
    Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: VISHAY-SILICONIX
    Inventor: Deva N. Pattanayak
  • Patent number: 8445368
    Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: May 21, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Alfred Goerlach, Ning Qu
  • Patent number: 8440536
    Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Publication number: 20130115746
    Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 9, 2013
    Applicant: International Rectifier Corporation
    Inventor: International Rectifier Corporation
  • Publication number: 20130109162
    Abstract: A method for incorporating radicals of a plasma into a substrate or a material on a semiconductor substrate using a remote plasma source. In one embodiment, a method for processing doped materials on a substrate surface is provided and includes forming a doped layer on a substrate and optionally cleaning the doped layer, such as by a wet clean process. The method also includes generating an ionized nitrogen plasma in a remote plasma source, wherein the ionized nitrogen plasma has an ion concentration within a range from about 0.001% to about 0.1%, de-ionizing the ionized nitrogen plasma while forming non-ionized nitrogen plasma. The method further includes flowing the non-ionized nitrogen plasma into a processing region within a processing chamber, forming a nitrided capping layer from an upper portion of the doped layer by exposing the doped layer within the processing region to the non-ionized nitrogen plasma during a stabilization process.
    Type: Application
    Filed: September 20, 2012
    Publication date: May 2, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Matthew S. Rogers, Martin A. Hilkene
  • Patent number: 8420496
    Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Publication number: 20130075855
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Publication number: 20130075748
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: EPOWERSOFT, INC.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 8405176
    Abstract: Disclosed is a phosphorus paste for diffusion that is used in continuous printing of a phosphorus paste for diffusion on a substrate by screen printing. The phosphorus paste for diffusion does not undergo a significant influence of ambient humidity on viscosity and has no possibility of thickening even after a large number of times of continuous printing. The phosphorus paste for diffusion is coated on a substrate by screen printing for diffusion layer formation on the substrate. The phosphorus paste for diffusion includes a doping agent containing phosphorus as a dopant for the diffusion layer, a thixotropic agent containing an organic binder and a solid matter, and an organic solvent. The doping agent is an organic phosphorus compound.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: March 26, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shintarou Tsukigata, Toshifumi Matsuoka, Kenji Yamamoto, Toyohiro Ueguri, Naoki Ishikawa, Hiroyuki Otsuka
  • Publication number: 20130069209
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided.
    Type: Application
    Filed: May 13, 2011
    Publication date: March 21, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kenji Fujita, Yasushi Funakoshi, Hiroyuki Oka, Satoshi Okamoto
  • Publication number: 20130069146
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
  • Patent number: 8399329
    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
  • Publication number: 20130062623
    Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.
    Type: Application
    Filed: February 24, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Yoshinori Tsuchiya, Takashi Shinohe
  • Patent number: 8394658
    Abstract: Disclosed are methods of forming multi-doped junctions, which utilize a nanoparticle ink to form an ink pattern on a surface of a substrate. From the ink pattern, a densified film ink pattern can be formed. The disclosed methods may allow in situ controlling of dopant diffusion profiles.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 12, 2013
    Assignee: Innovalight, Inc.
    Inventors: Giuseppe Scardera, Dmitry Poplavskyy, Michael Burrows, Sunil Shah
  • Patent number: 8390092
    Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
  • Publication number: 20130045557
    Abstract: An improved method of creating thermoelectric materials which have high electrical conductivity and low thermal conductivity is disclosed. In one embodiment, the thermoelectric material is made by depositing a porous film onto a substrate, introducing a dopant into the porous film and annealing the porous film to activate the dopant. In other embodiments, additional amounts of dopant may be introduced via subsequent ion implantations of dopant into the deposited porous film.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 21, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Xianfeng Lu, Ludovic Godet, Christopher Hatem, John Hautala
  • Patent number: 8367529
    Abstract: The invention concerns a method for preparing a NIII-V semiconductor. According to the invention, the method includes at least one step of doping a semiconductor of general formula AlxGa1-xN, wherein the atomic number x represents the number between 0 and 1 with a p-type electron-accepting dopant, as well as a co-doping step with a codopant capable of modifying the structure of the valency band. The invention also concerns a semiconductor as well as its use in electronics or optoelectronics. The invention further concerns a device as well as a diode using such a semiconductor.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: February 5, 2013
    Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche Scientifique (CNRS)
    Inventors: Bruno Daudin, Henri Mariette
  • Publication number: 20130029481
    Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
  • Publication number: 20130026646
    Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Alvin J. Joseph
  • Publication number: 20130025670
    Abstract: The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type impurity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of K, Na, Li, Ba, Sr, Ca, Mg, Be, Zn, Pb, Cd, V, Sn, Zr, Mo, La, Nb, Ta, Y, Ti, Ge, Te, and Lu.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Tetsuya SATO, Masato YOSHIDA, Takeshi NOJIRI, Yoichi MACHII, Mitsunori IWAMURO, Akihiro ORITA
  • Publication number: 20130023112
    Abstract: Methods for processing substrates are provided herein. In some embodiments, a method of processing a substrate may include implanting a substrate with a dopant in a first vacuum chamber; transferring the substrate to a second vacuum chamber at a first pressure below atmospheric; providing an inert gas to the second vacuum chamber to raise the pressure to a second pressure; pumping down the second vacuum chamber to a third pressure below the second pressure; and providing the inert gas to the second vacuum chamber to raise the pressure to a fourth pressure above the third pressure.
    Type: Application
    Filed: October 28, 2011
    Publication date: January 24, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Kartik SANTHANAM
  • Publication number: 20130020680
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20130023113
    Abstract: A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 24, 2013
    Applicants: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Tomoaki Hatayama
  • Patent number: 8354333
    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric
  • Patent number: RE44376
    Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gwo-Yuh Shiau, Ming Chyi Liu, Tzu-Hsuan Hsu, Chia-Shiung Tsai