Diffusion Of Impurity Material, E.g., Doping Material, Electrode Material, Into Or Out Of A Semiconductor Body, Or Between Semiconductor Regions; Interactions Between Two Or More Impurities; Redistribution Of Impurities (epo) Patents (Class 257/E21.135)
  • Publication number: 20110220199
    Abstract: An inkjet ink comprises phosphoric acid; one or more solvents for the phosphoric acid, preferably ethyl lactate and water; and one or more aprotic organic sulfoxides, preferably dimethyl sulfoxide (DMSO) or dimethyl sulfone (SMSO2). The inks do not leave a carbon residue on heating and so are suited to use in etching and/or doping silicon wafers, e.g. in the production of crystalline silicon solar cells.
    Type: Application
    Filed: October 30, 2009
    Publication date: September 15, 2011
    Applicant: CONDUCTIVE INKJET TECHNOLOGY LIMITED
    Inventors: Martyn John Robinson, Philip Gareth Bentley
  • Publication number: 20110217821
    Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 8, 2011
    Inventors: Huan-Ting Tseng, Chun-Hsien Huang, Hung-Chin Huang, Chen-Wei Lee
  • Publication number: 20110215412
    Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chengwen Pei, Roger A. Booth, JR., Kangguo Cheng, Joseph Ervin, Ravi M. Todi, Geng Wang
  • Publication number: 20110212602
    Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 1, 2011
    Inventors: Alfred GOERLACH, Ning Qu
  • Publication number: 20110204319
    Abstract: Nanostructures are doped to set conductivity characteristics. In accordance with various example embodiments, nanostructures such as carbon nanotubes are doped with a halogenated fullerene type of dopant material. In some implementations, the dopant material is deposited from solution or by vapor deposition, and used to dope the nanotubes to increase the thermal and/or electrical conductivity of the nanotubes.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 25, 2011
    Inventors: Ajay Virkar, Melburne C. Lemieux, Zhenan Bao
  • Publication number: 20110201188
    Abstract: An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is applied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 18, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Atul Gupta, Nicholas Bateman
  • Publication number: 20110195563
    Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
    Type: Application
    Filed: October 6, 2010
    Publication date: August 11, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Okuno, Yoichiro Tarui
  • Patent number: 7994017
    Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Kent Bertilsson, Andrei Konstantinov
  • Patent number: 7994061
    Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Publication number: 20110186805
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110186817
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: February 2, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110186806
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110186807
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110186969
    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 4, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric
  • Publication number: 20110186957
    Abstract: A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow.
    Type: Application
    Filed: October 28, 2010
    Publication date: August 4, 2011
    Inventor: Thilo Scheiper
  • Patent number: 7989329
    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 2, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle
  • Patent number: 7989293
    Abstract: A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 2, 2011
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jun Zeng
  • Patent number: 7989328
    Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: August 2, 2011
    Assignee: Spansion LLC
    Inventors: Seungmoo Choi, Sameer Haddad
  • Publication number: 20110165763
    Abstract: A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Giulliano Aloise
  • Publication number: 20110159673
    Abstract: Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 30, 2011
    Inventors: Hiroji Hanawa, Seon-Mee Cho, Majeed A. Foad
  • Publication number: 20110147813
    Abstract: A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10?8/(1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10?4(202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
    Type: Application
    Filed: November 11, 2010
    Publication date: June 23, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110147845
    Abstract: Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Prashant Majhi, Kausik Majumdar
  • Publication number: 20110139230
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.
    Type: Application
    Filed: June 3, 2010
    Publication date: June 16, 2011
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
  • Publication number: 20110136285
    Abstract: A method of manufacturing a stacked film includes; subjecting a semiconductor substrate to a radical oxidation reaction to form a radical oxide layer on a surface of the semiconductor substrate, annealing the radical oxide layer in a hydrogen atmosphere to convert the radical oxide layer to a first passivation layer, and disposing a second passivation layer on the first passivation layer.
    Type: Application
    Filed: May 13, 2010
    Publication date: June 9, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyoeng-Ki KIM
  • Publication number: 20110132423
    Abstract: A photovoltaic solar cell module comprises a plurality of bifacial solar cells and electrical conductors. Each bifacial solar cell comprises a plurality of bus-bar contacts. A phosphorous silicon glass layer is formed on one side of the bifacial cell by phosphorous diffusion, and a boron silicon glass layer is formed on the other side of the bifacial cell by boron diffusion. The phosphorous diffusion and the boron diffusion are conducted by a face-to-face diffusion method. The combination of the two gettering methods substantially increases the minority carrier life time of the bifacial solar cell.
    Type: Application
    Filed: October 11, 2007
    Publication date: June 9, 2011
    Applicant: Gamma Solar
    Inventors: Toshio Joge, Rodolfo J. Magasrevy
  • Publication number: 20110129990
    Abstract: Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.
    Type: Application
    Filed: July 26, 2010
    Publication date: June 2, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Tushar V. Mandrekar, Shankar Venkataraman, Zhong Qiang Hua, Manuel A. Hernandez
  • Publication number: 20110129975
    Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 2, 2011
    Inventor: Sang-Oh LEE
  • Patent number: 7951637
    Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: May 31, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weidman, Rohit Mishra, Michael P. Stewart, Kapila P. Wijekoon, Yonghwa Chris Cha, Tristan Holtam, Vinay Shah
  • Patent number: 7951695
    Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 31, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff, Ruiqi Tian
  • Publication number: 20110124187
    Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
  • Publication number: 20110121423
    Abstract: A mask for use in making a planar PN junction in a semiconductor device includes a central mask opening and a plurality of spaced apart concentric mask openings surrounding the central mask opening. The concentric mask openings each have a width less than a maximum dimension of the central mask opening. The central mask opening can be circular and the concentric mask openings can have a ring-shape. The mask can be used to form openings in a wafer layer for introducing an impurity to dope that wafer layer.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: Sensors Unlimited, Inc.
    Inventors: Keith Forsyth, Noah Clay
  • Publication number: 20110121424
    Abstract: Radiation-absorbing semiconductor devices and associated methods of making and using are provided. In one aspect, for example, a method for making a radiation-absorbing semiconductor device having enhanced photoresponse can include forming an active region on a surface of a low oxygen content semiconductor, and annealing the low oxygen content semiconductor to a temperature of from about 300° C. to about 1100° C., wherein the forming of the active region and the annealing of the low oxygen content semiconductor are performed in a substantially oxygen-depleted environment.
    Type: Application
    Filed: April 30, 2010
    Publication date: May 26, 2011
    Inventors: James Carey, Xia Li, Susan Alie, Martin U. Pralle
  • Patent number: 7947576
    Abstract: An aspect of the invention provides a method of manufacturing a method of manufacturing a semiconductor element comprises the steps of: growing epitaxially a semiconductor layer on top of a semiconductor substrate; forming a patterned portion of the grown semiconductor layer by forming a pattern by a patterning process on top of the grown semiconductor layer; removing a portion of the semiconductor layer other than the patterned portion by a first etching method with a first etchant; and immersing a resultant from the first etching method in a second etchant that etches only the semiconductor substrate by a second etching method thereby removing the substrate from the semiconductor layer.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: May 24, 2011
    Assignee: Oki Data Corporation
    Inventors: Tomoki Igari, Mitsuhiko Ogihara, Hiroyuki Fujiwara, Hironori Furuta, Takahito Suzuki, Tomohiko Sagimori, Yusuke Nakai
  • Publication number: 20110108985
    Abstract: A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillar patterns; depositing an insulating layer on the surface of the pillar pattern; removing a portion of the insulating layer located at one side of the pillar pattern to form a contact hole that exposes the pillar pattern; forming a barrier film in the contact hole; and forming a junction in the pillar pattern that contacts with the contact hole. In the method, when a buried bit line is formed, a diffusion barrier is formed in the contact hole and a junction is formed in the lower portion of the pillar pattern, thereby improving characteristics of the device.
    Type: Application
    Filed: June 15, 2010
    Publication date: May 12, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Seung Hwan KIM
  • Publication number: 20110108953
    Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 12, 2011
    Applicant: ABB Technology AG
    Inventors: Jan VOBECKY, Kati Hemmann, Hamit Duran, Munaf Rahimo
  • Publication number: 20110108095
    Abstract: A mask material composition that is used for diffusion barrier of an impurity diffusing component into a semiconductor substrate includes a siloxane resin (A1) containing a constituent unit represented by the following formula (a1): wherein R1 is a single bond or C1-C5 alkylene group; and R2 is a C6-C20 aryl group.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 12, 2011
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Motoki TAKAHASHI, Toshiro MORITA, Takaaki HIRAI
  • Patent number: 7939388
    Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Hisao Nagai, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20110101418
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: December 29, 2009
    Publication date: May 5, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Patent number: 7936047
    Abstract: A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: May 3, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vincenzo Enea, Cesare Ronsisvalle
  • Publication number: 20110095391
    Abstract: A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 28, 2011
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Huang-Lang Pai, Hung-Shern Tsai
  • Publication number: 20110089445
    Abstract: The invention concerns a method for preparing a NIII-V semiconductor. According to the invention, the method includes at least one step of doping a semiconductor of general formula AlxGa1-xN, wherein the atomic number x represents the number between 0 and 1 with a p-type electron-accepting dopant, as well as a co-doping step with a codopant capable of modifying the structure of the valency band. The invention also concerns a semiconductor as well as its use in electronics or optoelectronics. The invention further concerns a device as well as a diode using such a semiconductor.
    Type: Application
    Filed: March 6, 2007
    Publication date: April 21, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Bruno Daudin, Henri Mariette
  • Patent number: 7923368
    Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: April 12, 2011
    Assignee: Innovalight, Inc.
    Inventors: Mason Terry, Homer Antoniadis, Dmitry Poplavskyy, Maxim Kelman
  • Publication number: 20110079262
    Abstract: An embodiment of the present invention relates to a diffusing agent composition used in printing an impurity-diffusing component onto a semiconductor substrate, wherein the diffusing agent composition contains: a hydrolysis product of alkoxysilane (A); a component (B) containing at least one selected from the group consisting of a hydrolysis product of alkoxy titanium, a hydrolysis product of alkoxy zirconium, titania fine particle, and zirconia fine particle; an impurity-diffusing component (C); and an organic solvent (D).
    Type: Application
    Filed: October 4, 2010
    Publication date: April 7, 2011
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takashi KAMIZONO, Toshiro MORITA, Atsushi MUROTA, Motoki TAKAHASHI, Katsuya TANITSU, Takaaki HIRAI
  • Publication number: 20110065266
    Abstract: A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 17, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Bunji Mizuno
  • Publication number: 20110049622
    Abstract: A semiconductor device has an insulating film and an n-type buried layer. The insulating film is formed in a flat-shaped cavity formed inside a p-type semiconductor substrate and in a trench extending from a surface of the semiconductor substrate to the cavity. The buried layer is formed in surrounding regions of the cavity and the trench in the semiconductor substrate.
    Type: Application
    Filed: March 8, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyoshi Kitahara
  • Publication number: 20110045624
    Abstract: Disclosed is a phosphorus paste for diffusion that is used in continuous printing of a phosphorus paste for diffusion on a substrate by screen printing. The phosphorus paste for diffusion does not undergo a significant influence of ambient humidity on viscosity and has no possibility of thickening even after a large number of times of continuous printing. The phosphorus paste for diffusion is coated on a substrate by screen printing for diffusion layer formation on the substrate. The phosphorus paste for diffusion includes a doping agent containing phosphorus as a dopant for the diffusion layer, a thixotropic agent containing an organic binder and a solid matter, and an organic solvent. The doping agent is an organic phosphorus compound.
    Type: Application
    Filed: March 18, 2009
    Publication date: February 24, 2011
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shintarou Tsukigata, Toshifumi Matsuoka, Kenji Yamamoto, Toyohiro Ueguri, Naoki Ishikawa, Hiroyuki Otsuka
  • Publication number: 20110037125
    Abstract: A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ghavam G. Shahidi
  • Publication number: 20110039367
    Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 17, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Nicholas P.T. Bateman, Steven M. Anella, Benjamin B. Riordon, Atul Gupta
  • Patent number: 7888249
    Abstract: The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the solar cell. In another embodiment, two different species are successively implanted without breaking vacuum. In another embodiment, the substrate is implanted, then flipped such that it can be and implanted on both sides before being annealed. In yet another embodiment, one or more different masks are applied and successive implantations are performed without breaking the vacuum condition, thereby reducing the process time.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 15, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Atul Gupta, Paul Sullivan, Paul J. Murphy
  • Publication number: 20110033998
    Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 10, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier