With Group Iii-v Compound (epo) Patents (Class 257/E21.157)
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Patent number: 9786810Abstract: A method for forming optical devices. The method includes providing a gallium nitride substrate member having a crystalline surface region and a backside region. The method also includes subjecting the backside region to a laser scribing process to form a plurality of scribe regions on the backside region and forming a metallization material overlying the backside region including the plurality of scribe regions. The method removes at least one optical device using at least one of the scribe regions.Type: GrantFiled: May 4, 2015Date of Patent: October 10, 2017Assignee: Soraa Laser Diode, Inc.Inventors: Nicholas J. Pfister, James W. Raring, Mathew Schmidt
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Patent number: 8927348Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.Type: GrantFiled: May 12, 2009Date of Patent: January 6, 2015Assignee: Toyoda Gosei Co., Ltd.Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
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Patent number: 8872308Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.Type: GrantFiled: February 20, 2013Date of Patent: October 28, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
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Patent number: 8828790Abstract: A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer.Type: GrantFiled: August 20, 2009Date of Patent: September 9, 2014Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.Inventors: Ralf Preu, Andreas Grohe, Daniel Biro, Jochen Rentsch, Marc Hofmann, Jan-Frederik Nekarda, Andreas Wolf
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Patent number: 8633569Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.Type: GrantFiled: January 16, 2013Date of Patent: January 21, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
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Patent number: 8415180Abstract: Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11a of a gallium oxide substrate 11. After the growth of the buffer layer 13, while supplying a gas G2, which contains hydrogen and nitrogen, into a growth reactor 10, the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.Type: GrantFiled: March 1, 2010Date of Patent: April 9, 2013Assignees: Sumitomo Electric Industries, Ltd., Koha Co., Ltd.Inventors: Shin Hashimoto, Katsushi Akita, Kensaku Motoki, Shinsuke Fujiwara, Hideaki Nakahata
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Patent number: 8119492Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.Type: GrantFiled: July 10, 2009Date of Patent: February 21, 2012Assignee: United Microelectronics Corp.Inventor: Chun-Cheng Hsu
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Patent number: 7964424Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.Type: GrantFiled: November 5, 2008Date of Patent: June 21, 2011Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Patent number: 7939352Abstract: A method for fabricating a selective area metal bonding Si-based laser, optically or electrically pumped includes: forming a Si waveguide area and a bonding area in a Silicon-On-Insulator (SOI) wafer, and forming an isolating structure to separate the Si waveguide area from the bonding area; forming a metal multilayer for bonding, which also acts as ohmic contact layer in the laser when the laser is electrically pumped. A compound semiconductor optical gain structure is prepared by epitaxial growth and etched off the substrate. The compound semiconductor optical gain structure is aligned with the Si waveguide area in the SOI wafer and the compound semiconductor optical gain structure is bonded on the SOI wafer. The selective area metal bonding Si-based laser can be used as a light source in optoelectronic integration and Si photonics. The method may provide simple operation, flexibility, low cost, and low requirement for cleanness of manufacturing environments.Type: GrantFiled: August 11, 2009Date of Patent: May 10, 2011Assignee: Peking UniversityInventors: Guogang Qin, Tao Hong, Ting Chen, Guangzhao Ran, Weixi Chen
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Patent number: 7186632Abstract: In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020(1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.Type: GrantFiled: March 24, 2003Date of Patent: March 6, 2007Assignee: Elpida Memory, Inc.Inventors: Kazuo Ogawa, Kiyonori Ohyu, Kensuke Okonogi, Toshihiro Imamura, Keiichi Watanabe, Hiroyuki Ohta