Deposition Of Conductive Or Insulating Material For Electrode Conducting Electric Current (epo) Patents (Class 257/E21.159)
  • Patent number: 11164955
    Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 2, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Chiyu Zhu, Kiran Shrestha, Petri Raisanen, Michael Eugene Givens
  • Patent number: 10943830
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan
  • Patent number: 10615045
    Abstract: The invention provides: a resin as a material of a composition for forming an organic film having high filling and planarizing properties and etching resistance; the composition; and a patterning process using the composition. Provided is a composition for forming an organic film, including: (I) a resin having a structure shown by a general formula (1) in which a ring structure AR containing an aromatic ring and a spiro structure SP bonded to four of the ARs are alternately repeated in at least a portion of a repeating unit; and (II) an organic solvent.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 7, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Daisuke Kori, Tsutomu Ogihara
  • Patent number: 10516061
    Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Yen Yeh, Chih-Sheng Chang, Wilman Tsai, Yu-Ming Lin
  • Patent number: 10424513
    Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Il Park, Jeong Hoon Ahn, Joon-Nyung Lee
  • Patent number: 10354922
    Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Romain Lallement, Nelson Felix
  • Patent number: 10043973
    Abstract: Provided is a resistance random access memory device comprising: a first electrode; a second electrode; and a metallic oxide formed between the first electrode and the second electrode. Particularly, provided is a resistance random access memory device wherein the metallic oxide comprises a first crystal grain and a second crystal grain which differ from each other in crystallographic orientation and form a boundary area; wherein a surface is intervened between the first crystal grain and the second crystal grain in the boundary area, the surface having a surface index corresponding to a surface crystallographically consisting only of oxygen among the crystal faces of the metallic oxide; and wherein the boundary area is a surface in which an electrically conductive path is formed when voltage is applied between the first electrode and the second electrode.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 7, 2018
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Deok Hwang Kwon, Mi Young Kim
  • Patent number: 9934970
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 9923080
    Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, John R. Sporre, Stan Tsai, Ruilong Xie
  • Patent number: 9837414
    Abstract: After forming a stacked nanowire CMOS device including a first stacked nanowire array laterally surrounded by first epitaxial semiconductor regions, a second stacked nanowire array overlying the first stacked nanowire array and laterally surrounded by second epitaxial semiconductor regions, and a functional gate structure straddling over each semiconductor nanowire in the first and second stacked nanowire arrays, a common source/drain contact structure is formed on one side of the functional gate structure contacting one of the first epitaxial semiconductor regions and one of the second epitaxial semiconductor regions. A first local source/drain contact structure is formed on the opposite side of the functional gate structure contacting another of the first epitaxial semiconductor regions.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9776250
    Abstract: The present invention provides a silver nano-particle production method which is safe and simple also in terms of scaled-up industrial-level production, in a so-called thermal decomposition method in which a silver-amine complex compound is thermally decomposed to form silver nano-particles. A method for producing silver nano-particles comprising: mixing an aliphatic hydrocarbon amine and a silver compound in the presence of an alcohol solvent having 3 or more carbon atoms to form a complex compound comprising the silver compound and the amine; and thermally decomposing the complex compound by heating to form silver nano-particles.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: October 3, 2017
    Assignee: DAICEL CORPORATION
    Inventors: Yuki Iguchi, Kazuki Okamoto
  • Patent number: 9691864
    Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; forming at least one recess in the semiconductor substrate; the recess having a bottom and a sidewall; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space of the recess with a filling material for forming a filling structure in the recess; removing portions of the auxiliary structure from the sidewall of the recess so as to form at least one cavity between the filling structure and the sidewall of the recess; and sealing the cavity at the first side of the semiconductor substrate.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 27, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Robert Haase, Timothy Henson
  • Patent number: 9601652
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: March 21, 2017
    Assignee: SolAero Technologies Corp.
    Inventors: Tansen Varghese, Arthur Cornfeld
  • Patent number: 9537020
    Abstract: A method of manufacturing a solar cell electrode comprising steps of: preparing a semiconductor substrate, applying a conductive paste onto the light receiving side of the semiconductor substrate, wherein the conductive paste comprises (i) a conductive powder, (ii) a glass frit, (iii) an organic polymer comprising an elastomer and (iv) an organic solvent; and firing the applied conductive paste.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 3, 2017
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: John Donald Summers, Hikaru Uno
  • Patent number: 9245758
    Abstract: A method for fabricating a silicon-doped or boron-doped aluminum electrode is revealed. Aluminum target or aluminum paste prepared by selectively doped with silicon and/or boron is arranged at a silicon wafer with a passivation layer by physical deposition or screen printing. Then the doped aluminum layer is melted in linear or dot pattern to pass through the passivation layer and contact with the silicon wafer. Thus contact resistance between an aluminum back electrode and the silicon wafer of crystalline silicon solar cells is reduced and acceptor concentration on a surface layer of the silicon wafer is increased. Therefore the process speed is faster and the energy conversion efficiency of the solar cell is improved.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: January 26, 2016
    Assignee: Atomic Energy Council-Institute of Nuclear Energy Research
    Inventors: Wei-Yang Ma, Chien-Chang Chao, Guan-Lin Chen, Tsun-Neng Yang
  • Patent number: 9040324
    Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Eishi Tsutsumi, Koji Asakawa
  • Patent number: 9040383
    Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9034747
    Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Tae-Yoon Kim, Seung-Mi Lee, Woo-Young Park
  • Patent number: 9018090
    Abstract: Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Eric A. Joseph, Adam M. Pyzyna
  • Patent number: 9012323
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 21, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 9006102
    Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Yu Hong, Liu Huang, Zhao Feng
  • Patent number: 9006091
    Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
  • Patent number: 8980742
    Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 17, 2015
    Assignee: Wonik IPS Co., Ltd.
    Inventors: Jung Wook Lee, Young Hoon Park
  • Patent number: 8962476
    Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Jianmin Feng, Kang Chen
  • Patent number: 8951912
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 8952540
    Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Patent number: 8941094
    Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Nantero Inc.
    Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
  • Patent number: 8927418
    Abstract: Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, Chi-Yuan Chen, Hong-Mao Lee, Hui-Cheng Chang, Wei-Jung Lin, Bing-Hung Chen, Chia-Han Lai
  • Patent number: 8916462
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 23, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii
  • Patent number: 8907407
    Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Takahiro Oikawa
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8900981
    Abstract: A feedstock of semiconductor material is placed in a crucible. A closed sacrificial recipient containing a dopant material is placed in the crucible. The content of the crucible is melted resulting in incorporation of the dopant in the molten material bath. The temperature increase is performed under a reduced pressure.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 2, 2014
    Assignees: Apollon Solar, Siltronix
    Inventors: Maxime Forster, Erwann Fourmond, Jacky Stadler, Roland Einhaus, Hubert Lauvray
  • Patent number: 8895843
    Abstract: The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal and a lead-tellurium-boron-oxide dispersed in an organic medium.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 25, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Alan Frederick Carroll, Kenneth Warren Hang, Brian J. Laughlin, Kurt Richard Mikeska, Carmine Torardi, Paul Douglas Vernooy
  • Patent number: 8889979
    Abstract: The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal, and a lead-tellurium-lithium-titanium-oxide dispersed in an organic medium.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 18, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Alan Frederick Carroll, Kenneth Warren Hang, Brian J. Laughlin, Kurt Richard Mikeska, Carmine Torardi, Paul Douglas Vernooy
  • Patent number: 8889980
    Abstract: The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal, and a lead-tellurium-lithium-oxide dispersed in an organic medium.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 18, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Alan Frederick Carroll, Kenneth Warren Hang, Brian J. Laughlin, Kurt Richard Mikeska, Carmine Torardi, Paul Douglas Vernooy
  • Patent number: 8890315
    Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 18, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Won Kyoung Choi, Pandi C. Marimuthu
  • Patent number: 8889471
    Abstract: For solar cell fabrication, the addition of precursors to printable media to assist etching through silicon nitride or silicon oxide layer thus affording contact with the substance underneath the nitride or oxide layer. The etching mechanism may be by molten ceramics formed in situ, fluoride-based etching, as well as a combination of the two.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: November 18, 2014
    Assignee: Sichuan Yinhe Chemical Co., Ltd.
    Inventors: Ovadia Abed, Yunjun Li, James P. Novak, Samuel Kim, Patrick Ferguson
  • Patent number: 8883655
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignees: Intermoecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik
  • Patent number: 8884400
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Patent number: 8866268
    Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Shang-Yi Wu, Wen-Cheng Chien, Chia-Lun Tsai, Tien-Hao Huang
  • Patent number: 8836012
    Abstract: Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventor: Angela T. Hui
  • Patent number: 8835318
    Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Clemens Fitz, Jochen Poth, Kristin Schupke
  • Patent number: 8816503
    Abstract: A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten Ahrens, Johannes Baumgartl, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 8802564
    Abstract: A method of manufacturing a semiconductor component includes the steps of manufacturing of a wafer, applying structures of components on the wafer to form a wafer assembly, applying a metal coating on the wafer, removing the metal coating in non-contact areas of the components, applying surrounds on the edge areas of the components, arranging the wafer on a foil held by a clamping ring, separating the components of the wafer compound carried by the foil from one another, arranging a covering mask on the areas of the separated components carried by the foil which are not to be coated, applying a metal coating on the separate components covered with the mask, removal of the mask, and removal of the components from the foil and further processing the separate components wherein that applying a metal coating on the separate components covered by the mask takes place by means of thermal spraying.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: August 12, 2014
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Mathias Kock, Ronald Eisele
  • Patent number: 8802565
    Abstract: Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Hartig, Sivananda K. Kanakasabapathy, Soon-Cheon Seo, Raghavasimhan Sreenivasan
  • Patent number: 8796695
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 5, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8765601
    Abstract: Embodiments of the invention provide methods for forming materials on a substrate used for metal gate and other applications. In one embodiment, a method includes forming a cobalt stack over a barrier layer disposed on a substrate by depositing a cobalt layer during a deposition process, exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process, and repeating the cobalt deposition process and the plasma process to form the cobalt stack containing a plurality of plasma-treated cobalt layers. The method further includes exposing the cobalt stack to an oxygen source gas to form a cobalt oxide layer from an upper portion of the cobalt stack during a surface oxidation process and heating the remaining portion of the cobalt stack to a temperature within a range from about 300° C. to about 500° C. to form a crystalline cobalt film during a thermal annealing crystallization process.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yu Lei, Xinyu Fu, Anantha Subramani, Seshadri Ganguli, Srinivas Gandikota
  • Patent number: 8765586
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 1, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Peter Baars, Markus Lenski
  • Patent number: 8759220
    Abstract: A patterning process includes (1) forming, on a body to be processed on which a titanium-containing hard mask is formed, an organic underlayer film; (2) forming, on the organic underlayer film, a titanium-containing resist underlayer film having a titanium content of 10% to 60% by mass; (3) forming a photoresist film on the titanium-containing resist underlayer film; (4) forming a photoresist pattern by exposing the photoresist film and developing; (5) pattern-transferring onto the titanium-containing resist underlayer film by using the photoresist pattern as a mask; (6) pattern-transferring onto the organic underlayer film by using the titanium-containing resist underlayer film as a mask; and (7) removing the titanium-containing hard mask and the titanium-containing resist underlayer film by wet stripping method. A patterning process including removing a resist underlayer film using a wet stripper having a milder condition than the conventional stripper without causing damage to a body to be processed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 24, 2014
    Assignees: Shin-Etsu Chemical Co., Ltd., International Business Machines Corporation
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Seiichiro Tachibana, Yoshinori Taneda, Martin Glodde, Margaret C. Lawson, Wu-Song Huang
  • Patent number: 8748313
    Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 10, 2014
    Assignees: Semiconductor Manufaturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hsin Chin Chen