Selective Deposition (epo) Patents (Class 257/E21.171)
  • Patent number: 10651031
    Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 12, 2020
    Assignees: Samsung Electronics Co., Ltd., Adeka Corporation
    Inventors: Seung-min Ryu, Takanori Koide, Naoki Yamada, Jae-soon Lim, Tsubasa Shiratori, Youn-joung Cho
  • Patent number: 10566209
    Abstract: An etching method can protect a mask with a material having higher etching resistance to a silicon-containing film. The etching method is performed in a state that a processing target object is placed within a chamber main body. The etching method includes forming a tungsten film on the processing target object and etching the silicon-containing film of the processing target object. The forming of the tungsten film includes supplying a gaseous tungsten-containing precursor onto the processing target object; and generating plasma of a hydrogen gas to supply active species of hydrogen to the precursor on the processing target object. In the etching of the silicon-containing film, plasma of a processing gas containing fluorine, hydrogen and carbon is generated within the chamber main body.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 18, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu Nagatomo, Yoshihide Kihara
  • Patent number: 10566187
    Abstract: Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 18, 2020
    Assignee: Lam Research Corporation
    Inventors: Jun Qian, Hu Kang, Adrien LaVoie, Seiji Matsuyama, Purushottam Kumar
  • Patent number: 10529641
    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 10424477
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: September 24, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore
  • Patent number: 10388820
    Abstract: A metal organic chemical vapor deposition apparatus for a solar cell includes a deposition unit. The deposition unit includes a susceptor to be mounted with a substrate, and a shower head to prepare a reacting gas by mixing plural kinds of raw gases for deposition and supply the reacting gas to the susceptor.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 20, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Dongjoo You, Wonki Yoon, Heonmin Lee
  • Patent number: 10366878
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include net chemisorption of a self-assembled monolayer on the second surface to prevent deposition of the film on the second surface.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: July 30, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jessica Sevanne Kachian, Tobin Kaufman-Osborn, David Thompson
  • Patent number: 10355206
    Abstract: Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: July 16, 2019
    Assignee: Nantero, Inc.
    Inventors: C. Rinn Cleavelin, Claude L. Bertin, Thomas Rueckes
  • Patent number: 10340137
    Abstract: A method of forming a thin film is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to mix the adsorbed carbon-containing film with the material of the underlying substrate and form a mixed film.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter Ventzek, Alok Ranjan
  • Patent number: 10308673
    Abstract: Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as Sb—Te, Ge—Te, Ge—Sb—Te, Bi—Te, and Zn—Te thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as Sb—Se, Ge—Se, Ge—Sb—Se, Bi—Se, and Zn—Se thin films are also provided. Te and Se precursors of the formula (Te,Se)(SiR1R2R3)2 are preferably used, wherein R1, R2, and R3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 4, 2019
    Assignee: ASM International N.V.
    Inventors: Viljami Pore, Timo Hatanpaa, Mikko Ritala, Markku Leskelä
  • Patent number: 10074541
    Abstract: In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 11, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Jaakko Anttila
  • Patent number: 10008383
    Abstract: The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Ming Huang, Hsiu-Ting Chen, Shih-Chieh Chang
  • Patent number: 9947578
    Abstract: Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing a substrate, within a first substrate process chamber, to a plasma formed from a first gas comprising a metal organic tungsten precursor gas or a fluorine-free tungsten halide precursor to deposit a tungsten liner layer, wherein the tungsten liner layer is deposited atop a dielectric layer and within a feature formed in a first surface of the dielectric layer of a substrate; transferring the substrate to a second substrate process chamber without exposing the substrate to atmosphere; and exposing the substrate to a second gas comprising a tungsten fluoride precursor to deposit a tungsten fill layer atop the tungsten liner layer.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 17, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yu Lei, Vikash Banthia, Kai Wu, Xinyu Fu, Yi Xu, Kazuya Daito, Feiyue Ma, Pulkit Agarwal, Chi-Chou Lin, Dien-Yeh Wu, Guoqiang Jian, Wei V. Tang, Jonathan Bakke, Mei Chang, Sundar Ramamurthy
  • Patent number: 9935005
    Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 3, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Kurtis Leschkies, Steven Verhaverbeke
  • Patent number: 9935264
    Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Eugene P. Marsh, Stefan Uhlenbrock, Chet E. Carter, Scott E. Sills
  • Patent number: 9905412
    Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 9837310
    Abstract: A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9831451
    Abstract: Provided is a thin film transistor array substrate, including a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor pattern formed on the gate insulating layer and including a channel region overlapping the gate electrode, a source electrode and a drain electrode formed on the semiconductor pattern and facing each other with a first opening exposing the channel region therebetween, a first protective layer formed on the gate insulating layer to cover the source electrode, the drain electrode and the semiconductor pattern and a metal oxide layer formed along a surface of the first protective layer.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Je-Hun Lee
  • Patent number: 9793139
    Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Keerti Shukla, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • Patent number: 9704716
    Abstract: In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 11, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Jaakko Anttila
  • Patent number: 9613908
    Abstract: Implementations described herein generally relate to the formation of a silicon and aluminum containing layer. Methods described herein can include positioning a substrate in a process region of a process chamber; delivering a process gas to the process region, the process gas comprising an aluminum-containing gas and a silicon-containing gas; activating a reactant gas comprising a nitrogen-containing gas, a hydrogen containing gas, or combinations thereof; delivering the reactant gas to the process gas to create a deposition gas that deposits a silicon and aluminum containing layer on the substrate; and purging the process region. The above elements can be performed one or more times to deposit an etch stop stack.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 4, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Deenesh Padhi, Yihong Chen, Kelvin Chan, Abhijit Basu Mallick, Alexandros T. Demos, Mukund Srinivasan
  • Patent number: 9613854
    Abstract: A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Hsiang-Huan Lee, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou
  • Patent number: 9536782
    Abstract: A tungsten film forming method includes: supplying a tungsten chloride gas as a source material of tungsten and a reducing gas towards a substrate to be processed under a depressurized atmosphere to cause reaction between the tungsten chloride gas and the reducing gas while heating the substrate to be processed, such that a main tungsten film is directly formed on a surface of the substrate to be processed without forming an initial tungsten film for nucleus generation.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takanobu Hotta, Yasushi Aiba, Koji Maekawa
  • Patent number: 9412602
    Abstract: In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 9, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Jaakko Anttila
  • Patent number: 9330970
    Abstract: The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ting-Chu Ko
  • Patent number: 8993455
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Patent number: 8860184
    Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 8746174
    Abstract: A discharge surface treatment apparatus supplies an electrode material to a surface of a treatment target member by generating pulsating discharges across an inter-electrode gap to form a coating of the electrode material, and includes a switching element that turns application of a voltage from a power source to the inter-electrode gap on/off, a capacitance element that is connected to the switching element in parallel with the inter-electrode gap, an inductance element that is connected in series between both of the switching element and the capacitance element and the inter-electrode gap, and a control unit that includes a function of periodically performing on/off so that an induced electromotive force generated in the inductance element due to a change in the current of discharge generated across the inter-electrode gap can be used as a voltage that induces the next discharge.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: June 10, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshikazu Nakano, Akihiro Goto
  • Patent number: 8685850
    Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu
  • Patent number: 8680682
    Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 8618003
    Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Eastman Kodak Company
    Inventors: Mitchell S. Burberry, David H. Levy
  • Patent number: 8546257
    Abstract: Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tobias Kraus, Laurent Malaquin, Heiko Wolf
  • Patent number: 8517769
    Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 27, 2013
    Assignee: GlobalFoundries Inc.
    Inventors: Sean X. Lin, Ming He, Xunyuan Zhang, Larry Zhao
  • Patent number: 8513116
    Abstract: Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: August 20, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Amit Khandelwal, Madhu Moorthy, Avgerinos V. Gelatos, Kai Wu
  • Patent number: 8492273
    Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: George Bryce, Simone Severi, Peter Verheyen
  • Patent number: 8482043
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • Patent number: 8466052
    Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
  • Patent number: 8450197
    Abstract: Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8344513
    Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 8324098
    Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Mehmet Emin Aklik, Thomas James Moutinho
  • Patent number: 8278216
    Abstract: The present invention provides methods of selectively depositing refractory metal and metal nitride cap layers onto copper lines inlaid in a dielectric layer. The methods result in formation of a cap layer on the copper lines without significant formation on the surrounding dielectric material. The methods typically involve exposing the copper lines to a nitrogen-containing organo-metallic precursor and a reducing agent under conditions that the metal or metal nitride layer is selectively deposited. In a particular embodiment, an amino-containing tungsten precursor is used to deposit a tungsten nitride layer. Deposition methods such as CVD or ALD may be used.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: October 2, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Glenn Alers, Nerissa Draeger, Michael Carolus, Julie Carolus, legal representative
  • Patent number: 8268724
    Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Houssam Jomaa, Christine Tsau
  • Patent number: 8258626
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 4, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8211799
    Abstract: Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Amit Khandelwal, Madhu Moorthy, Avgerinos V. Gelatos, Kai Wu
  • Patent number: 8207044
    Abstract: Methods of fabricating an oxide layer on a semiconductor substrate are provided herein. The oxide layer may be formed over an entire structure disposed on the substrate, or selectively formed on a non-metal containing layer with little or no oxidation of an exposed metal-containing layer. The methods disclosed herein may be performed in a variety of process chambers, including but not limited to decoupled plasma oxidation chambers, rapid and/or remote plasma oxidation chambers, and/or plasma immersion ion implantation chambers. In some embodiments, a method may include providing a substrate comprising a metal-containing layer and non-metal containing layer; and forming an oxide layer on an exposed surface of the non-metal containing layer by exposing the substrate to a plasma formed from a process gas comprising a hydrogen-containing gas, an oxygen-containing gas, and at least one of a supplemental oxygen-containing gas or a nitrogen-containing gas.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: June 26, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Rajesh Mani, Norman Tam, Timothy W. Weidman, Yoshitaka Yokota
  • Patent number: 8168546
    Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: May 1, 2012
    Assignee: Eastman Kodak Company
    Inventor: David H. Levy
  • Patent number: 8168537
    Abstract: A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: May 1, 2012
    Assignee: NXP B.V.
    Inventors: Joerg Jasper, Ute Jasper
  • Patent number: 8101521
    Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: January 24, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Juwen Gao, Lana Hiului Chan, Panya Wongsenakhum
  • Patent number: 8058729
    Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: November 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Brenda D Kraus, Eugene P. Marsh