Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

Abstract: Exemplary methods of semiconductor processing may include delivering a deposition precursor into a processing region of a semiconductor processing chamber. The methods may include depositing a layer of material on a substrate housed in the processing region of the semiconductor processing chamber. The processing region may be maintained at a first pressure during the deposition. The methods may include extending a baffle within the processing region. The baffle may modify a flow path within the processing region. The methods may include forming a plasma of a treatment or etch precursor within the processing region of the semiconductor processing chamber. The processing region may be maintained at a second pressure during the forming. The methods may include treating the layer of material deposited on the substrate with plasma effluents of the treatment precursor. The processes may be cycled any number of times.

Abstract: The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate having a trench therein; a first layer covering the bottom and the sidewall of the trench; and a second layer covering the surface of the first layer, wherein the step coverage of the second layer is different from the step coverage of the first layer. The embodiment of the invention is conducive to obtaining a multi-layer structure with preset step coverage.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of less than or about 1,000 W. The methods may include depositing a silicon-containing material on the one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features at a rate of at least 2:1 relative to deposition on the exposed regions of the substrate.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: A method for forming a barrier layer in a semiconductor structure is disclosed. A substrate having a dielectric layer is provided. The dielectric layer is exposed to a precursor having a first metal, and a first ammonia treatment is performed. A first purge operation is performed, a second ammonia treatment is performed after the first purge operation, and a second purge operation is performed after the second ammonia treatment to form the barrier layer on the dielectric layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a recess structure in a substrate and forming a first semiconductor layer over the recess structure. The process of forming the first semiconductor layer can include doping first and second portions of the first semiconductor layer with a first n-type dopant having first and second doping concentrations, respectively. The second doping concentration can be greater than the first doping concentration. The method can further include forming a second semiconductor layer over the second portion of the first semiconductor layer. The process of forming the second semiconductor layer can include doping the second semiconductor layer with a second n-type dopant.

Abstract: Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

Abstract: Chemical vapor deposition (CVD) processes which use a ruthenium precursor of formula R1R2Ru(0), wherein R1 is an aryl group-containing ligand, and R2 is a diene group-containing ligand and a reducing gas a described. The CVD can include oxygen after an initial deposition period using the ruthenium precursor and reducing gas. The method can provide selective Ru deposition on conductive materials while minimizing deposition on non-conductive or less conductive materials. Further, the subsequent use of oxygen can significantly improve deposition rate while minimizing or eliminating oxidative damage of the substrate material. The method can be used to form Ru-containing layers on integrated circuits and other microelectronic devices.

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

Abstract: Provided are a precursor supply unit, a substrate processing system, and a method of fabricating a semiconductor device using the same. The precursor supply unit may include an outer container, an inner container provided in the outer container and used to store a precursor source, a gas injection line having an injection port, which is provided below the inner container and in the outer container and is used to provide a carrier gas into the outer container, and a gas exhaust line having an exhaust port, which is provided below the inner container and in the outer container and is used to exhaust the carrier gas in the outer container and a precursor produced from the precursor source.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

Abstract: Atomic layer deposition (ALD) methods and barrier films are disclosed. A method of performing ALD includes placing a substrate proximal an electrode coupled to a power supply, exposing the substrate to an oxygen-containing gas or a nitrogen-containing gas at or below 0.8 Torr, and applying, with the power supply, a voltage to the electrode of at least 700 Volts to induce a plasma state in the oxygen-containing gas or the nitrogen-containing gas proximal the substrate. High quality barrier films can be made with the methods.

Abstract: Methods of depositing a film by atomic layer deposition are described. The methods comprise exposing a substrate surface to a first process condition comprising a first reactive gas and a second reactive gas and exposing the substrate surface to a second process condition comprising the second reactive gas. The first process condition comprises less than a full amount of the second reactive gas for a CVD process.

Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure.

Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a source region and a drain region in a semiconductor substrate, and a bit line over the source region. The semiconductor device also includes a first epitaxial structure over the drain region, and a capacitor contact over the first epitaxial structure. A bottom surface of the capacitor contact is higher than a bottom surface of the bit line.

Abstract: The present disclosure relates to a method for preparing a semiconductor device. The method includes forming a source region and a drain region in a semiconductor substrate, and forming a bit line over the source region. The method also includes growing a first epitaxial structure over the drain region. A top surface of the first epitaxial structure is higher than a bottom surface of the bit line. The method further includes forming a capacitor contact over the first epitaxial structure.

Abstract: Selective ruthenium and selective ruthenium oxide may be used in single damascene processes and/or dual damascene processes to form BEOL metallization layers and vias of an electronic device. A selective ruthenium liner may be formed to achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias.

Abstract: When a titanium-containing gas and an oxidizing gas, or a silicon-containing gas and a nitriding gas, are alternately supplied from a gas supplier and radio frequency power is supplied to each of a first electrode and a second electrode from a power supply, parallel to the supply of the oxidizing gas or the nitriding gas, so as to generate plasma and to perform a film formation, a magnitude of the radio frequency power to be supplied to each of the first electrode and the second electrode is controlled.

Abstract: A method for deposition of a thin film onto a substrate is provided. The method includes providing a source precursor containing on or more of elements constituting the thin film, generating a transient species from the source precursor, and depositing a thin film onto the substrate from the transient species. The transient species being a reactive intermediate that has a limited lifetime in a condensed phase at or above room temperature.

Abstract: An array substrate includes a substrate as well as a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a conductive structure sequentially formed thereon. The first insulating layer has a first opening communicated with a through hole of the substrate. The first conductive layer includes a first ring pattern extending from top of the first insulating layer into the first opening. The second insulating layer has a second opening communicated with the first opening. The second conductive layer includes a second ring pattern extending from top of the second insulating layer into the second opening. The first ring pattern laterally protrudes toward an axis of the through hole from the second ring pattern. The conductive structure extends from above the second insulating layer to a bottom surface of the substrate through the first and second openings and the through hole.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: Implementations disclosed herein generally relate to systems and methods of protecting a substrate support in a process chamber from cleaning fluid during a cleaning process. The method of cleaning the process chamber includes positioning in the process chamber a cover substrate above a substrate support and a process kit that separates a purge volume from a process volume. The method of cleaning includes flowing a purge gas in the purge volume to protect the substrate support and flowing a cleaning fluid to a process volume above the cover substrate, flowing the cleaning fluid in the process volume to an outer flow path, and to an exhaust outlet in the chamber body. The purge volume is maintained at a positive pressure with respect to the process volume to block the cleaning fluid from the purge volume.

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

Abstract: A system includes a chamber, a support structure disposed in the chamber, and one or more heads. The support structure is configured to support and position a substrate. The one or more heads includes an energy source coupled to a near-field transducer for providing localized energy towards the support structure at select locations within the chamber.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

Abstract: A laminate includes a substrate made of an organic polymer having a functional group containing an oxygen atom or a nitrogen atom, a functional layer bonded to the functional group of the organic polymer contained in the substrate and formed by an atomic layer deposition process, and an overcoat layer provided to cover the functional layer and containing transition metal atoms. Because the adhesion between the substrate and the functional layer is improved and the functional layer is protected by the overcoat layer, it is possible to achieve both improved gas barrier properties and/or improved durability against an environmental stress such as heat, humidity and the like.

Abstract: Provided is a method of depositing tungsten, in which depositing a tungsten nucleation layer is formed by performing a unit cycle at least once, wherein the unit cycle includes an absorption step in which a first process gas is provided on a substrate such that at least a portion of the first process gas is absorbed on the substrate, a first purge step in which a purge gas is provided on the substrate to purge the first process gas which has not been absorbed on the substrate, a reaction step in which a gas containing tungsten is provided on the substrate as a second process gas to form a unit deposition film on the substrate, a second purge step in which a purge gas is provided on the substrate to purge a reaction by-product on the substrate, a processing step in which a processing gas containing a hydrogen (H) element is provided on the substrate to reduce the concentration of an impurity in the unit deposition film, and a third purge step in which a purge gas is provided on the substrate to purge the proce

Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):

Abstract: Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.

Abstract: An etching method can protect a mask with a material having higher etching resistance to a silicon-containing film. The etching method is performed in a state that a processing target object is placed within a chamber main body. The etching method includes forming a tungsten film on the processing target object and etching the silicon-containing film of the processing target object. The forming of the tungsten film includes supplying a gaseous tungsten-containing precursor onto the processing target object; and generating plasma of a hydrogen gas to supply active species of hydrogen to the precursor on the processing target object. In the etching of the silicon-containing film, plasma of a processing gas containing fluorine, hydrogen and carbon is generated within the chamber main body.

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract: A metal organic chemical vapor deposition apparatus for a solar cell includes a deposition unit. The deposition unit includes a susceptor to be mounted with a substrate, and a shower head to prepare a reacting gas by mixing plural kinds of raw gases for deposition and supply the reacting gas to the susceptor.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include net chemisorption of a self-assembled monolayer on the second surface to prevent deposition of the film on the second surface.

Abstract: Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.

Abstract: A method of forming a thin film is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to mix the adsorbed carbon-containing film with the material of the underlying substrate and form a mixed film.

Abstract: Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as Sb—Te, Ge—Te, Ge—Sb—Te, Bi—Te, and Zn—Te thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as Sb—Se, Ge—Se, Ge—Sb—Se, Bi—Se, and Zn—Se thin films are also provided. Te and Se precursors of the formula (Te,Se)(SiR1R2R3)2 are preferably used, wherein R1, R2, and R3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.

Abstract: In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.

Abstract: The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region.

Abstract: Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing a substrate, within a first substrate process chamber, to a plasma formed from a first gas comprising a metal organic tungsten precursor gas or a fluorine-free tungsten halide precursor to deposit a tungsten liner layer, wherein the tungsten liner layer is deposited atop a dielectric layer and within a feature formed in a first surface of the dielectric layer of a substrate; transferring the substrate to a second substrate process chamber without exposing the substrate to atmosphere; and exposing the substrate to a second gas comprising a tungsten fluoride precursor to deposit a tungsten fill layer atop the tungsten liner layer.

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.

Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.