Abstract: A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved.

Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

Abstract: A transistor device includes a high electron mobility field effect transistor (HEMT) and a protection device. The HEMT has a source, a drain and a gate. The HEMT switches on and conducts current from the source to the drain when a voltage applied to the gate exceeds a threshold voltage of the HEMT. The protection device is monolithically integrated with the HEMT so that the protection device shares the source and the drain with the HEMT and further includes a gate electrically connected to the source. The protection device conducts current from the drain to the source when the HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device. The protection device has a lower threshold voltage than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT.

Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

Abstract: A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode.

Abstract: In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process.

Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

Abstract: A method of making a transistor is disclosed. The method starts with applying a first photoresist and performing a first etching of the first side of a gate where the gate includes an oxide layer formed over a substrate and a conductive material formed over the oxide layer. The first etching is followed by implanting an impurity region into the substrate while using the first photoresist and the conductive material as a mask making the implantation of the impurity region self-aligned to the gate. The implantation is followed by applying a second photoresist and performing a second etching of the second side of the gate.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.

Abstract: Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: Generally, the present disclosure is directed to forming conductive metal fill materials in replacement gate electrodes using reduced deposition temperatures. One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor layer, the sacrificial gate structure including a dummy gate electrode, and forming a gate cavity by removing at least the dummy gate electrode from above the semiconductor layer. The disclosed method further includes forming a work-function material of a replacement metal gate electrode in the gate cavity, and forming a conductive metal fill material in the gate cavity and above the work-function material, wherein forming the conductive metal fill material includes performing a material deposition process at a temperature below approximately 450° C.

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages.

Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Abstract: An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 ? in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.

Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Abstract: A semiconductor memory device and a method for fabricating the sane are disclosed. In the semiconductor device, an insulation film of a drain region is formed to have a thick thickness in a local region such that it improves Hot Carrier Degradation (HCD) characteristics. The semiconductor device includes a first insulation film formed over a semiconductor substrate, a gate formed over the first insulation film, and a second insulation film located at a specific region between the first insulation film and the gate.

Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.

Abstract: A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract: Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.

Abstract: A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric.

Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.

Abstract: A floating gate transistor, comprising source and drain electrodes covered by a first dielectric separated by a channel, a floating gate electrode on the first dielectric arranged over the channel, an interlayer at least partially comprised of a semiconductor material and an organic material, and a control gate on the interlayer electrically coupled to the gate electrode.

Abstract: A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.

Abstract: Systems and methods are presented for controlling formation of a silicide region. A selective etch layer is utilized to control formation of a trench opening, and further can be utilized to open up a trench to facilitate correct exposure of an active Si region to subsequently form a silicide. Issues regarding over-dimension, under-dimension, and misalignment of a trench are addressed. The selective etch material is chosen to facilitate control of the trench formation and also to enable removal of the selective etch layer without affecting any adjacent structures/material. The selective etch layer can be an oxide, for example aluminum oxide, Al2O3. The selective etch layer can be utilized to prevent formation of silicide in a channel beneath a raised source/drain.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure.

Abstract: A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

Abstract: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.

Abstract: One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.

Abstract: A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.

Abstract: A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has an elongate shape and is oriented along the first direction. The first functional gate is separated from the dummy gate in a second direction perpendicular to the first direction. A first conductive contact is formed on the first functional gate. The semiconductor device includes a second functional gate formed over the substrate. The second functional gate has an elongate shape and is oriented along the first direction. The second functional gate is aligned with and physically separated from the dummy gate in the first direction. A second conductive contact is formed on the second functional gate.

Abstract: According to one exemplary implementation, an integrated circuit (IC) includes a first memory cell transistor of a read only memory (ROM) array, the first memory cell transistor including a first metal gate of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor of the ROM array, the second memory cell transistor including a second metal gate of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric.

Abstract: A semiconductor device and method of forming. According to one embodiment, the method includes providing a substrate with defined device regions and having an interface layer thereon, depositing a first high-k film on the interface layer, and performing a heat-treatment to form a modified interface layer. The method further includes depositing a first threshold voltage adjustment layer, removing the first threshold voltage adjustment layer from the second device region, depositing a second high-k film above the first high-k film, and depositing a gate electrode film on the second high-k film. A first gate stack is defined that contains the modified interface layer, the first high-k film, the first threshold voltage adjustment layer, the second high-k film, and the gate electrode film, and a second gate stack is defined that contains the modified interface layer, the first high-k film, the second high-k film, and the gate electrode film.

Abstract: A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.