Conductor Layer Next To The Insulator Is Single Metal, E.g., Ta, W, Mo, Al (epo) Patents (Class 257/E21.202)
  • Patent number: 11380775
    Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Patent number: 11322394
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11158721
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11024719
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki Sawabe, Nobuyoshi Saito, Junji Kataoka, Tomomasa Ueda, Keiji Ikeda
  • Patent number: 10868176
    Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 15, 2020
    Assignee: Sony Corporation
    Inventor: Yasushi Tateshita
  • Patent number: 10770587
    Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventor: Mark T. Bohr
  • Patent number: 10636692
    Abstract: To improve peelability, yield in a peeling step, and yield in manufacturing a flexible device. A peeling method is employed which includes a first step of forming a peeling layer containing tungsten over a support substrate; a second step of forming, over the peeling layer, a layer to be peeled formed of a stack including a first layer containing silicon oxynitride and a second layer containing silicon nitride in this order and forming an oxide layer containing tungsten oxide between the peeling layer and the layer to be peeled; a third step of forming a compound containing tungsten and nitrogen in the oxide layer by heat treatment; and a fourth step of peeling the peeling layer from the layer to be peeled at the oxide layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiji Yasumoto, Masataka Sato, Shingo Eguchi, Kunihiko Suzuki
  • Patent number: 10553699
    Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Patent number: 10541128
    Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10504721
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 10, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 10490662
    Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventor: Mark T. Bohr
  • Patent number: 10304685
    Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 28, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chao-Sheng Cheng
  • Patent number: 10211309
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first N-type work function metal layer on the capping layer, forming a second N-type work function metal layer on the first N-type work function metal layer, and forming a metal electrode layer on the second N-type work function metal layer. The second N-type work function metal layer has a Ti/Al atomic ratio greater than the Ti/Al atomic ratio of the first N-type work function metal layer. The second work function metal layer having a higher Ti/Al atomic ratio will not absorb appreciable oxygen from the atmosphere, so that oxygen will not be available to the first work function metal layer, thereby reducing the oxidation level of the first work function metal layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10074725
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 9922974
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Patent number: 9679944
    Abstract: An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 13, 2017
    Assignee: SK hynix Inc.
    Inventor: Jung-Nam Kim
  • Patent number: 9524905
    Abstract: A nitridation step applied to a tungsten via in a first silicon oxide layer forms a tungsten nitride layer on an exposed top surface of the tungsten via. Subsequently, a second silicon oxide layer is formed over the first silicon oxide layer and the tungsten via. Subsequently, an opening is formed through the second silicon oxide layer to expose at least part of the silicon nitride layer. Subsequently, a wet clean step is performed.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Ryusuke Mikami, Yasushi Matsumoto, Yosuke Nakashima
  • Patent number: 9466605
    Abstract: A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 11, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Kai-Yao Shih, Ssu-Ting Wang, Chi-Kai Feng, Tzung-Hua Ying, Te-Yuan Yin
  • Patent number: 9397189
    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
  • Patent number: 9293334
    Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Kuo, Chung-Liang Cheng, Hsien-Ming Lee, Weng Chang
  • Patent number: 9245955
    Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 26, 2016
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Pietro Montanini
  • Patent number: 9202695
    Abstract: A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 1, 2015
    Assignee: IMEC
    Inventor: Mitsuhiro Togo
  • Patent number: 9190481
    Abstract: A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate electrode layer on the substrate. The method also includes forming a dielectric film on the substrate and the dummy gate structure; and performing a thermal annealing process onto the dielectric film to increase the density of the interlayer dielectric film. Further, the method includes planarizing the dielectric film having the increased density until the top surface of the dummy gate structure is exposed; and forming a dense layer having an increased density on the dielectric film having the increased density. Further, the method also includes removing the dummy gate dielectric layer and the dummy gate electrode layer to form an opening; and forming a gate dielectric layer and a gate electrode layer sequentially in the opening.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 8969195
    Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Steven P. Barkyoumb, Edward C. Cooney, III, Thomas L. McDevitt, William J. Murphy, David C. Strippe
  • Patent number: 8753946
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United States
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8753947
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8716118
    Abstract: A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Unoh Kwon, Vijay Narayanan
  • Patent number: 8633494
    Abstract: A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Masato Nishimori, Toshihide Kikkawa
  • Patent number: 8546212
    Abstract: A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one gate trench and a first inter-layer dielectric layer are formed on the substrate. A work function metallic layer is then formed in the gate trench. A first contact hole is then formed in the first inter-layer dielectric layer. A main conductive layer is formed in the gate trench and the first contact hole simultaneously.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Hao Su, Hang Hu, Hong Liao
  • Patent number: 8536041
    Abstract: A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8450772
    Abstract: A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: May 28, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heon Yong Chang, Suk Kyoung Hong, Hae Chan Park
  • Patent number: 8431472
    Abstract: Methods is provided for forming a CMOS device. The method includes providing a substrate and depositing a gate stack on the substrate. The gate stack includes a gate dielectric and a dummy gate including polycrystalline silicon (polySi). The method also includes depositing a dielectric layer on the substrate after depositing the gate stack on the substrate. The method further includes substituting the dummy gate with a metal without first removing the dummy gate.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 30, 2013
    Assignee: Globalfoundries, Inc.
    Inventor: Chang Seo Park
  • Patent number: 8399317
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Patent number: 8399289
    Abstract: An apparatus includes a first solid electrode on a substrate, a polyelectrolyte layer over a part of the first solid electrode, a second solid electrode on a portion of the polyelectrolyte layer, and an anchoring layer on the part of the first solid electrode. The polyelectrolyte layer is either chemically bonded to the anchoring layer or has a thickness of less than about 20 nanometers.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: March 19, 2013
    Assignee: Alcatel Lucent
    Inventors: Oleksandr Sydorenko, Nikolai B. Zhitenev
  • Patent number: 8394714
    Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Lexmark International, Inc.
    Inventor: Byron V. Bell
  • Patent number: 8383481
    Abstract: In one embodiment, a method of manufacturing a semiconductor memory device is disclosed. The method can comprise forming a tunnel insulating film on a substrate, forming a charge storage layer including a conductor on the tunnel insulating film, forming an isolation trench which isolate the charge storage layer and the tunnel insulating film in the substrate, embedding an isolation insulating film in the isolation trench, removing a native oxide film which is formed on a surface of the charge storage layer, and forming an insulating film on a surface of the isolation insulating film and the surface of the charge storage layer. The process from the removing the native oxide film to the forming the insulating film carried out in a manufacture apparatus in which an oxygen concentration is controlled.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayuki Tanaka
  • Patent number: 8377771
    Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Brian McIntrye, Michael K. Harper, Subhash M. Joshi
  • Patent number: 8354313
    Abstract: In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Dechao Guo, Siddarth A. Krishnan, Ramachandran Muralidhar
  • Patent number: 8313991
    Abstract: A method is provided for fabricating a high-K metal gate MOS device. The method includes providing a semiconductor substrate having a surface region, a gate oxide layer on the surface region, a sacrificial gate electrode on the gate oxide layer, and a covering layer on the sacrificial gate electrode, an inter-layer dielectric layer on the semiconductor substrate and the sacrificial gate electrode. The method also includes planarizing the inter-layer dielectric layer to expose a portion of the covering layer atop the sacrificial gate electrode, implanting nitrogen ions into the inter-layer dielectric layer until a depth of implantation is deeper than a thickness of the portion of the covering layer atop the sacrificial gate electrode and polishing the inter-layer dielectric layer to expose a surface of the sacrificial gate electrode, removing the sacrificial gate electrode, and depositing a metal gate.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: November 20, 2012
    Assignee: Semiconductor Manufacturing International Corp
    Inventors: Li Jiang, Mingqi Li
  • Patent number: 8241977
    Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: August 14, 2012
    Assignee: GlobalFoundries Inc.
    Inventors: Thilo Scheiper, Andy Wei, Sven Beyer
  • Patent number: 8232604
    Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8133768
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 13, 2012
    Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the Unites States National Aeronautics and Space Administration
    Inventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8026539
    Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 27, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Hargrove, Frank Bin Yang, Rohit Pal
  • Publication number: 20110193126
    Abstract: A semiconductor light-emitting element comprises: a semiconductor substrate; a semiconductor laminated structure including a first conductivity-type semiconductor layer, an active layer, a second conductivity-type semiconductor layer, and a contact layer that are sequentially laminated on the semiconductor substrate; a ridge portion in an upper portion of the semiconductor laminated structure; a channel portion adjoining opposite sides of the ridge portion; a terrace portion adjoining opposite sides of the channel portion and, with the channel portion, sandwiching the ridge portion; a first insulating film covering the channel portion and having openings on the ridge portion and the terrace portion; a single-layer adhesive layer on the first insulating film; a Pd electrode on the ridge portion and a part of the single-layer adhesive layer and electrically connected to the contact layer of the ridge portion; and a second insulating layer covering a portion not covered by the Pd electrode of the single-layer ad
    Type: Application
    Filed: October 26, 2010
    Publication date: August 11, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takafumi Oka, Shinji Abe, Kazushige Kawasaki, Hitoshi Sakuma
  • Patent number: 7919379
    Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Rashmi Jha, Sivananda Kanakasabapathy, Xi Li, Renee T. Mo, Vijay Narayanan, Vamsi Paruchuri, Mark T. Robson, Kathryn T. Schonenberg, Michelle L. Steen, Richard Wise, Ying Zhang
  • Patent number: 7892961
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Cheng-Tung Lin, Liang-Gi Yao
  • Publication number: 20110034022
    Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring 124), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).
    Type: Application
    Filed: October 15, 2010
    Publication date: February 10, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Junichi Nakamura
  • Patent number: 7863124
    Abstract: A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different nFET and pFET gate electrode materials.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Chudzik, Bruce B. Doris, William K. Henson, Hongwen Yan, Ying Zhang
  • Patent number: 7803682
    Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto
  • Patent number: 7745278
    Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri