Chemical Etching (epo) Patents (Class 257/E21.219)
  • Patent number: 7932118
    Abstract: A mechanical component production method of a MEMS/NEMS structure from a monocrystalline silicon substrate includes forming anchoring zones in one face of the substrate. A lower protective layer, non-silicon, obtained by epitaxy from the face of the substrate is formed on the face. A silicon layer obtained by epitaxy from the lower protective layer is formed on the lower protective layer. An upper protective layer is formed on the silicon layer. The upper protective, silicon and lower protective layers are etched according to a pattern defining the component, until the substrate is reached, providing access routes to the substrate. A protective layer is formed on the walls formed by the etching in the epitaxied silicon layer. The component is released by isotropic etching of the substrate from the access routes, wherein the isotropic etching does not attack the lower and upper protective layers and the protective layer of the walls.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: April 26, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Philippe Robert, Valérie Nguyen
  • Publication number: 20110092074
    Abstract: A liquid agent for the surface treatment of monocrystalline wafers, which contains an alkaline etching agent and also at least one low-volatile organic compound. Systems of this type can be used both for the cleaning, damage etch and texturing of wafer surfaces in a single etching step and exclusively for the texturing of silicon wafers with different surface quality, whether it now be wire-sawn wafers with high surface damage or chemically polished surfaces with minimum damage density.
    Type: Application
    Filed: June 2, 2010
    Publication date: April 21, 2011
    Applicant: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Kuno Mayer, Mark Schumann, Daniel Kray, Teresa Orellana Peres, Jochen Rentsch, Martin Zimmer, Elias Kirchgässner, Eva Zimmer, Daniel Biro, Arpad Mihai Rostas, Filip Granek
  • Publication number: 20110092051
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Application
    Filed: December 23, 2010
    Publication date: April 21, 2011
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Publication number: 20110076855
    Abstract: There is provided a resin laminate having a layer construction of a first inorganic material layer/insulating layer/second inorganic material layer or a layer construction of an inorganic material layer/insulating layer, wherein the insulating layer has a multi-layer structure of two or more resin layers of a core insulating layer and an adhesive insulating layer. In this case, the resin laminate has the adhesive insulating layer which can realize optimal etching, is suitable for etching by a wet process, and has excellent adhesion. At least one of the layers constituting the insulating layer is formed of a polyimide resin which comprises repeating units represented by formula (1) and has a glass transition point of 150 to 360° C. and is dissolvable in a basic solution at a rate of more than 3 ?m/min, preferably more than 5 ?m/min, and most preferably more than 8 ?m/min.
    Type: Application
    Filed: October 25, 2010
    Publication date: March 31, 2011
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Katsuya SAKAYORI, Shigeki KAWANO, Hiroko AMASAKI, Hidetsugu TAZAWA, Kazunari IKEDA, Kouhei OHNO
  • Publication number: 20110070739
    Abstract: A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Haining S. Yang
  • Publication number: 20110070744
    Abstract: The current invention describes a process and texturing solution for texturing a crystalline silicon substrate to provide a light trapping surface within a crystalline silicon based solar cell. In an embodiment the texturing process includes a pre-treatment of hydrofluoric acid followed by the application of a texturing solution that includes potassium hydroxide (KOH) and butanol. The application of the texturing solution may be followed by a hydrofluoric acid post-treatment. A combinatorial method of optimizing the textured surface of a crystalline silicon substrate is also described.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 24, 2011
    Inventors: Zhi-Wen Sun, Minh Anh Nguyen
  • Patent number: 7910490
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Publication number: 20110065281
    Abstract: A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 17, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: DAVID GAO, Fumitake Mieno
  • Publication number: 20110059618
    Abstract: This invention relates to a method for texturing a silicon surface and silicon wafers made by the method, where the method comprises immersing the wafers in an alkaline solution at pH>10, and applying a potential difference between the wafer and a platinum electrode in the electrolyte in the range of +10 to +85 V.
    Type: Application
    Filed: March 12, 2009
    Publication date: March 10, 2011
    Applicant: Norut Narvik AS
    Inventors: Ingemar Olefjord, Timothy C. Lommasson
  • Publication number: 20110053345
    Abstract: An object is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; and etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left.
    Type: Application
    Filed: August 19, 2010
    Publication date: March 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Keitaro IMAI
  • Publication number: 20110049651
    Abstract: Provided are a three-dimensional (3D) MEMS structure and a method of manufacturing the same. The method of manufacturing the 3D MEMS structure having a floating structure includes depositing a first etch mask on a substrate, etching at least two regions of the first etch mask to expose the substrate, and forming at least one step in the etched region, partially etching the exposed region of the substrate using the first etch mask, and forming at least two grooves, depositing a second etch mask on a sidewall of the groove, and performing an etching process to connect lower regions of the at least two grooves to each other, and forming at least one floating structure.
    Type: Application
    Filed: August 10, 2010
    Publication date: March 3, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Chang Han JE
  • Patent number: 7897491
    Abstract: Methods and apparatuses for selective epitaxial formation of films separately inject reactive species into a CVD chamber. The methods are particularly useful for selective deposition using volatile combinations of precursors and etchants. Formation processes include simultaneous supply of precursors and etchants for selective deposition, or sequential supply for cyclical blanket deposition and selective etching. In either case, precursors and etchants are provided along separate flow paths that intersect in the relatively open reaction space, rather than in more confined upstream locations.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: March 1, 2011
    Assignee: ASM America, Inc.
    Inventor: Matthias Bauer
  • Publication number: 20110042687
    Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Alfred Grill, Chun-yung Sung
  • Publication number: 20110045673
    Abstract: The invention relates to a method for manufacturing a silicon surface with a pyramidal structure, in which a silicon wafer containing the silicon surface is dipped into an etching solution. To produce a pyramidal structure that is as homogeneous as possible, according to the invention it is proposed that the silicon surface be treated with ozone prior to coming into contact with the etching solution.
    Type: Application
    Filed: March 12, 2009
    Publication date: February 24, 2011
    Applicant: Rena GmbH
    Inventors: Juergen Schweckendiek, Ahmed Abdelbar Eljaouhari
  • Publication number: 20110039406
    Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 17, 2011
    Applicant: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20110039411
    Abstract: A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 ?m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 17, 2011
    Applicant: SILTRONIC AG
    Inventors: Bertram Moeckel, Helmut Franke
  • Publication number: 20110034012
    Abstract: In one embodiment, a patterning method is disclosed. The method includes applying an uncured imprint material containing a first curing agent and a second curing agent onto a substrate. The method includes pressing a template against the imprint material. The method includes reacting the first curing agent with the template pressed against the imprint material. The method includes stripping the template from the imprint material. In addition, the method includes reacting the second curing agent.
    Type: Application
    Filed: July 15, 2010
    Publication date: February 10, 2011
    Inventor: Yoshihito KOBAYASHI
  • Publication number: 20110028000
    Abstract: A method for selectively etching a silicon-containing film on a silicon substrate is disclosed. The method includes depositing a silicon-containing film on the silicon substrate. The method further includes baking the silicon-containing film to create a densified silicon-containing film, wherein the densified film has a first thickness. The method also includes exposing the silicon substrate to an aqueous solution comprising NH4F and HF in a ratio of between about 6:1 and about 100:1, at a temperature of between about 20° C. and about 50° C., and for a time period of between about 30 seconds and about 5 minutes; wherein between about 55% and about 95% of the densified silicon-containing film is removed.
    Type: Application
    Filed: September 24, 2010
    Publication date: February 3, 2011
    Inventors: Elena Rogojina, Eric Rosenfeld, Dmitry Poplavskyy
  • Publication number: 20110021032
    Abstract: The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al1-x-zGaxInzAs1-ySby with 0<x<1, 0<y<1, 0?z<1 and 0<x+z<1, a process for wet acid etching of intrinsic, n-doped or p-doped Al1-x-zGaxInzAs1-ySby with 0<x<1, 0<y<1 and 0?z<1 and 0<x+z<1, and a semiconductor structure prepared by wet acid etching of Al1-x-zGaxInzAs1-ySby with 0<x<1, 0<y?1, 0?z<1 and 0<x+z<1. The etchant comprises: organic acid; oxidizing agent; hydrofluoric acid.
    Type: Application
    Filed: January 12, 2010
    Publication date: January 27, 2011
    Inventors: Renato BUGGE, Bjørn-Ove FIMLAND
  • Publication number: 20110014771
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.
    Type: Application
    Filed: January 25, 2010
    Publication date: January 20, 2011
    Inventors: Vance Dunton, Raghuveer S. Makala, Michael Chan
  • Publication number: 20110014794
    Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 20, 2011
    Inventors: Arnd KAELBERER, Helmut Baumann, Roland Scheuerer, Heribert Weber
  • Patent number: 7871936
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: January 18, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Publication number: 20110006284
    Abstract: A photonic structure includes a plurality of annealed, substantially smooth-surfaced ellipsoids arranged in a matrix. Additionally, a method of producing a photonic structure is provided. The method includes providing a semiconductor material, providing an etch mask comprising a two-dimensional hole array, and disposing the etch mask on at least one surface of the semiconductor material. The semiconductor material is then etched through the hole array of the etch mask to produce holes in the semiconductor material and thereafter applying a passivation layer to surfaces of the holes. Additionally, the method includes repeating the etching and passivation-layer application to produce a photonic crystal structure that contains ellipsoids within the semiconductor material and annealing the photonic crystal structure to smooth the surfaces of the ellipsoids.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Hans S. Cho, David A. Fattal, Theodore I. Kamins
  • Patent number: 7867910
    Abstract: The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Carmelo F. Scrudato, George Y. Gu, Loren L. Hahn, Steven B. Herschbein
  • Publication number: 20100327393
    Abstract: A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . ) are formed through the dielectric stack (3) for passage of etchant for etching a plurality of overlapping sub-cavities (4-1,2 . . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity (4) in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventors: Walter B. Meinel, Kalin V. Lazarov, Brian E. Goodlin
  • Publication number: 20100330811
    Abstract: An improved method of forming a via hole is provided. This method makes it possible to form a via hole having a highly accurate processed shape in an insulating body. The insulating body has a multi-layer structure made of different kinds of insulating layers. The insulating body has, for example, a first insulating layer and a second insulating layer on the first insulating layer. The first insulating layer is provided on a lower wiring layer. The method includes a step of forming a first through hole in the second insulating layer by dry etching. The first through hole reaches the first insulating layer. The side wall of the first through hole defines an exposed portion of the second insulating layer. The bottom of the first through hole defines an exposed portion of the first insulating layer.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Takeshi Nagao
  • Publication number: 20100317195
    Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing CaXb and CdHXe to perform a pre-treatment on the patterned hard mask and the dielectric layer, in which a, b, d and e from CaXb and CdHXe are integers and X represents halogen atom; and performing an etching process to transfer the aperture into the dielectric layer.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 16, 2010
    Inventors: Chih-Wen Feng, Pei-Yu Chou, Jiunn-Hsiung Liao, Ying-Chih Lin, Feng-Yi Chang, Meng-Chun Lee
  • Publication number: 20100311247
    Abstract: A method and device for treating silicon wafers. In a first step, the silicon wafers (22) are conveyed flat along a continuous, horizontal conveyor belt (12, 32) and nozzles (20) or the like spray an etching solution (21) from the top onto the wafers to texture them, only little etching solution (21) being applied to the silicon wafers (22) from below. In a second step, the silicon wafers (22), which are aligned as in the first step, are wetted exclusively from below with the etching solution (35) to etch-polish them.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 9, 2010
    Applicant: Gebr. Schmid GmbH & Co.
    Inventor: Heinz Kappler
  • Publication number: 20100311243
    Abstract: A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Inventor: Guomin Mao
  • Publication number: 20100304570
    Abstract: Disclosed is a semiconductor etching method whereby a semiconductor layer made of, for example, a Group III-V nitride semiconductor resistant to etching can be etched by a relatively easier process. This etching method comprises forming a metal-fluoride layer 3 at least as a part of an etching mask on the surface of a base structure (1,2); treating the metal-fluoride layer with a liquid; and etching the base structure using the metal-fluoride layer as a mask.
    Type: Application
    Filed: October 31, 2008
    Publication date: December 2, 2010
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Hideyoshi Horie, Takashi Fukada
  • Patent number: 7842521
    Abstract: The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: November 30, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Scott J. Limb
  • Publication number: 20100297848
    Abstract: The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2) ranges from 1:3.5 to 1:4.5; and applying a second etch feed gas of nitrogen trifluoride (NF3), helium (He) and chlorine (Cl2), in which the ratio of nitrogen trifluoride (NF3) to chlorine (Cl2) ranges from 1:5 to 2:5 and the ratio of helium (He) to nitrogen trifluoride (NF3) and chlorine (Cl2) ranges from 1:3 to 1:1.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew J. Breitwisch, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott, Brandon Yee
  • Publication number: 20100297852
    Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and
    Type: Application
    Filed: May 25, 2010
    Publication date: November 25, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-gon Jung, Suk-joo Lee, Woo-sung Han, Seong-woon Choi
  • Publication number: 20100294352
    Abstract: Layered metal structures are patterned to form a surface with some locations having an alloy along the top surface at some locations and the original top metal layer at other locations along the surface. The alloy and original top metal layer can be selected to have differential etching properties such that the pattern of the alloy or original metal can be selectively etched to form a patterned metal interconnect. In general, the patterning is performed by localized heating that drives formation of the alloy at the heated locations. The metal patterning can be useful for solar cell applications as well as for electronics applications, such as display applications.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 25, 2010
    Inventors: Uma Srinivasan, Neeraj Pakala, William A. Sanders, Henry Hieslmair
  • Publication number: 20100288330
    Abstract: Solar cells are manufactured from P-type doped monocrystalline or polycrystalline silicon ingots by sawing wafers and applying an N-type doping. The wafers can be improved by etching them, especially in a plasma assisted process, with fluorine, carbonyl fluoride, SF6 or NF3. Hereby, the surface is roughened so that the degree of light reflection is reduced, cracks caused from the sawing operation are prevented from proliferation, and glass-like phosphorus-containing oxide coatings caused by phosphorus doping are removed.
    Type: Application
    Filed: April 28, 2008
    Publication date: November 18, 2010
    Applicant: SOLVAY FLUOR GMBH
    Inventor: Marcello Riva
  • Patent number: 7829467
    Abstract: Semiconductor wafers are cut from a crystal and subjected to a series of processing steps in which material is removed from a front side and a rear side of the semiconductor wafers, comprising the following processing steps: a mechanical processing step, an etching step in which the semiconductor wafers are oxidized and material is removed from the front side of the wafers with the aid of a gaseous etchant containing hydrofluoric acid at a temperature of 20 to 70° C., and a polishing step in which the front side of the semiconductor wafer is polished, the processing steps in which the front side of the semiconductor wafer is polished causing material removal which does not amount to more than 5 ?m in total.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: November 9, 2010
    Assignee: Siltronic AG
    Inventors: Maximilian Stadler, Günter Schwab, Diego Feijóo, Karlheinz Langsdorf
  • Patent number: 7829475
    Abstract: The present invention relates to control of copper contamination to semiconductor substrates upon operation of a heat treatment apparatus which is a semiconductor manufacturing apparatus and which is constructed with quartz products having been contaminated with copper when machined. The quartz product is placed in a heating atmosphere on the stage where it is not still used for a heat treatment for semiconductor substrates. Baking gases including a hydrogen chloride gas and a gas for enhancing activity of the hydrogen chloride gas, for example, an oxygen gas, are then supplied to the quartz product. Consequently, the copper concentration in the region from the surface to the 30 ?m depth of the quartz product can be controlled below 20 ppb, preferably below 3 ppb. The baking process may be carried out before or after assembling the quartz product into the heat treatment apparatus.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: November 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Katsuhiko Anbai, Masayuki Oikawa, Tetsuya Shibata, Yuichi Tani
  • Patent number: 7825026
    Abstract: A gas inlet is disposed in a lower portion of a reaction chamber, a copper substrate is disposed in an upper portion thereof, and a tungsten catalytic body heated to 1600° C. is disposed midway between the two. Ammonia gas introduced from the gas inlet is decomposed by the tungsten catalytic body, a chemical species generated by the decomposition reacts with a surface of the copper substrate, and reduces and removes a contaminant on the copper surface, and a Cu3N thin film is formed on the copper substrate surface. This Cu3N film has the action of a film which prevents the oxidation of copper. This Cu3N film is thermally decomposed and removed when heated to temperatures of not less than 300° C., leaving a clean copper surface behind.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: November 2, 2010
    Assignee: Kyushu Institute of Technology
    Inventors: Akira Izumi, Masamichi Ishihara
  • Publication number: 20100269903
    Abstract: Provided are: a safe, low-cost method of producing a polycrystalline silicon substrate excellent in photoelectric conversion efficiency by which a uniform, fine uneven structure suited to a solar cell can be simply formed on the surface of the polycrystalline silicon substrate; and a polycrystalline silicon substrate having a uniform, fine, pyramid-shaped uneven structure so that its reflectance can be significantly reduced. The uneven structure is formed on the surface of the polycrystalline silicon substrate by etching the polycrystalline silicon substrate with an alkaline etching solution containing at least one kind selected from the group consisting of a carboxylic acid having 1 or more and 12 or less carbon atoms and each having at least one carboxyl group in one molecule, and salts of the acids.
    Type: Application
    Filed: November 28, 2008
    Publication date: October 28, 2010
    Applicants: MIMASU SEMICONDUCTOR INDUSTRY CO., LTD., WAKO PURE CHEMICAL INDUSTRIES, LTD.
    Inventors: Masato Tsuchiya, Ikuo Mashimo, Yoshimichi Kimura, Takehisa Kato, Masahiko Kakizawa
  • Publication number: 20100273321
    Abstract: A system to form a wet soluble lithography layer on a semiconductor substrate includes providing the substrate, depositing a first layer comprising a first material on the substrate, and depositing a second layer comprising a second material on the substrate. In an embodiment, the first material comprises a different composition than the second material and one of the first layer and the second layer includes silicon.
    Type: Application
    Filed: April 27, 2009
    Publication date: October 28, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Wei Wang, Ching-Yu Chang
  • Publication number: 20100272389
    Abstract: A semiconductor optical element having a mesa structure formed by wet etching, includes a mesa structure having a ridge-type mesa structure or a high-mesa-type mesa structure, the mesa structure being disposed on a semiconductor substrate, and an extended mesa on the semiconductor substrate, the extended mesa being connected to a corner of the mesa structure and being the same material as the mesa structure.
    Type: Application
    Filed: January 21, 2010
    Publication date: October 28, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Yamatoya, Yoshimichi Morita, Chikara Watatani
  • Publication number: 20100267225
    Abstract: A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Inventors: Hyo-san Lee, Bo-un Yoon, Kun-tack Lee, Dae-hyuk Kang, Jeong-nam Han, Jung-jae Myung, Hyung-pyo Hong, Hun-pyo Hong
  • Publication number: 20100267242
    Abstract: In a method of vapor etching, a sample that includes a first layer atop of and in contact with a second layer which is atop of and in contact with a third layer, wherein at least the first and second layers are comprised of different materials. The sample is etched by a vapor etchant under first process conditions that cause at least a part of the first layer to be fully removed while leaving the third layer and the second layer underlying the removed part of the first layer substantially unetched. The sample is then etched by the same or a different vapor etchant under second process conditions that cause at least the part of the second layer exposed by the removal of the at least part of the first layer to be fully removed while leaving the third layer underlying the removed part of the second layer substantially unetched.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 21, 2010
    Applicant: XACTIX, INC.
    Inventors: Kyle S. Lebouitz, David L. Springer, John J. Neumann, JR.
  • Publication number: 20100267240
    Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 21, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Publication number: 20100264518
    Abstract: The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the alternated arrangement of the concave and convex portions, a mesh structure of consistent construction is formed on the grinding surface of the wafer, making it possible to cut down greatly the interference and influence generated by the texture of grinding surface, and improve substantially the structural strength of the grinding surface for a consistent quality of wafer with better applicability and industrial benefits.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Inventor: Shura LEE
  • Publication number: 20100264510
    Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
    Type: Application
    Filed: October 20, 2008
    Publication date: October 21, 2010
    Applicants: DENSO CORPORATION, Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Ohtsuki, Mitsutaka Katada, Nobuhiko Noto, Hiroshi Takeno, Kazuhiko Yoshida
  • Publication number: 20100267244
    Abstract: The present invention concerns an improved method for treating germanium surfaces in order to reveal crystal defects.
    Type: Application
    Filed: November 5, 2008
    Publication date: October 21, 2010
    Inventor: Alexandra Abbadie
  • Publication number: 20100261351
    Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
    Type: Application
    Filed: November 20, 2009
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: James A. Culp, Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Paterson, Jed H. Rankin
  • Patent number: 7811889
    Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Leo Mathew
  • Publication number: 20100255682
    Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.
    Type: Application
    Filed: March 22, 2010
    Publication date: October 7, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Douglas M. Trickett, Atsushi Yamashita