Abstract: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction.

Abstract: A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.

Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

Abstract: A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.

Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order.

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

Abstract: Methods of fabricating a memory device can include forming a plurality of wordlines on a semiconductor substrate. A ground select line can be formed on a first side of the wordlines. A string select line can be formed on a second side of the wordlines. The wordlines can extend between the ground select line and the string select line. First spacers may be formed between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines. Second spacers can be formed on sidewalls of the ground select line and the string select line displaced from the first spacers. The second spacers can be formed from a different material than the first spacers.

Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end

Abstract: A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion; an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion. The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.

Abstract: The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties.

Abstract: A memory cell is provided. The memory cell comprises a first wire shaped channel structure; and a charge trapping structure surrounding the perimeter surface of the first wire shaped channel structure, the charge trapping structure comprising two charge trapping partial to structures, wherein each charge trapping partial structure is formed of a different material capable of storing electrical charges. Methods of manufacturing the memory cell are also provided.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

Abstract: A nonvolatile semiconductor memory device includes a source region and a drain region spaced from each other in a surface of a semiconductor layer, a tunnel insulating film provided on the semiconductor layer between the source region and the drain region, a charge storage film provided on the tunnel insulating film, a block insulating film provided on the charge storage film, and a control gate electrode provided on the block insulating film. The block insulating film is made of (Rm1?xLnx)2?yAlyO3+?, where Ln is one or more selected from Pr, Tb, Ce, Yb, Eu, and Sm, Rm is one or more selected from La, Nd, Gd, Dy, Ho, Er, Tm, Lu, Y, and Sc, 0<x<0.167 (but 0<x<0.333 if Ln is Pr, and 0<x<0.292 if Ln is Tb), 0.95?y?1.20, and 0???x(2?y)/2 (but ?x(2?y)/2???0 if Ln is Yb, Eu, and Sm, 0???x(2?y)/3 if Ln is Pr, and 0???3x(2?y)/14 if Ln is Tb).

Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

Abstract: Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor.

Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-? material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.

Abstract: In one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a resist on a subject layer containing silicon. The method can etch the subject layer using the resist as a mask and with a gas containing a halogen element, which is introduced into a processing chamber. After the etching of the subject layer, the method can slim a planner size of the resist with oxygen gas and a gas containing a halogen element, which are introduced into the same processing chamber.

Abstract: Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers.

Abstract: By removing an interlayer insulating film from a memory cell region in which a plurality of bit line diffusion layers and a plurality of word lines are formed, a trench which exposes the plurality of word lines and the sidewall insulating film is formed on the memory cell region. Thereafter, an ultraviolet light blocking film is formed on the exposed word lines and sidewall insulating film to fill the trench. Here, in the step of forming the trench, the trench is formed so that an end of the trench in a direction in which the bit line diffusion layers are extended is located on a word line located at an outermost portion of the memory cell region.

Abstract: A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.

Abstract: A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits.

Abstract: A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structures.

Abstract: A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa.

Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.

Abstract: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.

Abstract: Provided is a charge trapping layer which has excellent memory characteristics, a method of forming the charge trapping layer, a nonvolatile memory device using the charge trapping layer, and a method of fabricating the nonvolatile memory device, in which a hybrid nanoparticle which is obtained by mixing a nanoparticle having an excellent programming characteristic with a nanoparticle having an excellent erasing characteristic is used as the charge trapping layer. The charge trapping layer for use in the nanoparticle is discontinuously formed between a tunneling oxide film and a control oxide film, and includes at least two different kinds of numerous nanoparticles.

Abstract: A nonvolatile semiconductor memory device and a method for manufacturing the same that may include forming an isolation pattern in a substrate, and then etching a portion of the isolation pattern to expose a portion of an active region of the substrate, and then forming high-density second-type ion implantation regions spaced apart at both edges of the active region by performing a tilted ion implantation process, and then forming a high-density first-type ion implantation region as a bit line in the active region, and then forming an insulating layer on the substrate including the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the isolation pattern, and then forming a metal interconnection as a word line on the insulating layer pattern and extending in a direction perpendicular to bit line.

Abstract: A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.

Abstract: A nonvolatile memory cell comprising a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate with a gate insulation film interposed between them, a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate on both sides of the gate electrode, a channel region positioned in the surface layer of the semiconductor substrate between the pair of impurity diffusion layers, a charge storage layer formed on a surface of at least one impurity diffusion layer and along a side wall of the gate electrode, and a charge storage layer electrode laminated on the charge storage layer.

Abstract: Disclosed is a method for fabricating a nonvolatile memory device having a stacked gate structure in which a floating gate, a charge blocking layer, and a control gate are sequentially stacked. The method includes forming a first conductive layer for floating gate over a substrate; forming a charge blocking layer and a second conductive layer for control gate over a resulting structure including the first conductive layer; forming an etch mask pattern over the second conductive layer; performing a primary etch process on the second conductive layer until the charge blocking layer is exposed; forming a passivation layer on a sidewall of the second conductive layer exposed by the primary etch process; and performing a secondary etch process on the charge blocking layer and the first conductive layer.

Abstract: Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a plurality of device isolation regions being disposed in an upper-layer portion of the semiconductor substrate, and dividing the upper-layer portion into a plurality of semiconductor portions extending in a first direction; a plurality of charge storage films which are disposed on one of the plurality of the semiconductor portions and spaced apart from one another in the first direction; a block insulating film disposed covering the plurality of charge storage films; and a word electrode disposed on the block insulating film for each of rows of the plurality of charge storage films arranged in a second direction intersecting the first direction, wherein the block insulating film is disposed continuously in the first direction and in the second direction.

Abstract: Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.

Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.

Abstract: The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

Abstract: A method of preparing a floating trap type device on a substrate is described. The method comprises forming a trap layer structure on a substrate, and modifying a composition of one or more layers in the trap layer structure by exposing the trap layer structure to a gas cluster ion beam (GCIB).