Vapor Phase Etching (epo) Patents (Class 257/E21.222)
  • Patent number: 10056264
    Abstract: Provided herein are ALE methods of removing III-V materials such as gallium nitride (GaN) and related apparatus. In some embodiments, the methods involve exposing the III-V material to a chlorine-containing plasma without biasing the substrate to form a modified III-V surface layer; and applying a bias voltage to the substrate while exposing the modified III-V surface layer to a plasma to thereby remove the modified III-V surface layer. The disclosed methods are suitable for a wide range of applications, including etching processes for trenches and holes, fabrication of HEMTs, fabrication of LEDs, and improved selectivity in etching processes.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 21, 2018
    Assignee: Lam Research Corporation
    Inventors: Wenbing Yang, Tomihito Ohba, Samantha Tan, Keren Jacobs Kanarik, Jeffrey Marks, Kazuo Nojiri
  • Patent number: 9666580
    Abstract: A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 30, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshitaka Nagasato, Hidemoto Tomita, Masakazu Kanechika
  • Patent number: 9666706
    Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Kyoung-yeon Kim, Sang-moon Lee, Ki-ha Hong, Eui-chul Hwang
  • Patent number: 9660143
    Abstract: The present invention relates to a substrate having an upper surface that is not parallel to a reference plane, wherein the substrate may include the upper surface or an upper layer which is inclined or inflexed. In addition, the present invention relates to a light emitting diode comprising an active layer that is not parallel to a reference plane. The light emitting diode of the present invention may be characterized in that the active layer is inflexed. Furthermore, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed. Moreover, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed and inclined. Through the configuration, the size of a chip is identically maintained, and the area of the active layer for emitting light is increased.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 23, 2017
    Inventor: Hongseo Yom
  • Patent number: 9419094
    Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Kyoung-yeon Kim, Sang-moon Lee, Ki-ha Hong, Eui-chul Hwang
  • Patent number: 9385001
    Abstract: A P-N junction gate high electron mobility transistor (HEMT) device with a self-aligned gate structure and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. A gate layer is formed on the barrier layer, the gate layer comprising a P-type group III-V semiconductor material suitable for depleting the carriers of a current conducting channel at the heterojunction when the HEMT device is off. A gate electrode comprising indium tin oxide (ITO) is formed on the gate layer, the gate electrode and the gate layer having substantially the same length.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 5, 2016
    Assignee: Toshiba Corporation
    Inventors: Yongxiang He, Xinyu Zhang
  • Patent number: 8940640
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Xiao
  • Patent number: 8669190
    Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Togo, Hiroaki Sano
  • Patent number: 8524602
    Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: September 3, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Jen Wang
  • Publication number: 20130210204
    Abstract: According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to TE (K) given in a following equation; and a step of etching the polycrystalline silicon by dry etching with an etching gas containing CF4 and O2, T E = - 0.114 ? x + 0.0556 k × ln ? { ( 1 - r / d ) × - 6.27 ? x + 5.38 - 2.01 ? x + 3.11 } where d (nm) is etching amount of the polycrystalline silicon, r (nm) is surface roughness of the polycrystalline silicon after the etching, x is ratio of flow rate of CF4 gas to sum of flow rate of the CF4 gas and flow rate of O2 gas, and k (eV/K) is Boltzmann constant.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 15, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takayuki SAKAI
  • Patent number: 8476158
    Abstract: A GaN substrate storage method of storing, within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m3, a GaN substrate (1) having a planar first principal face (1m), and whose plane orientation in an arbitrary point (P) along the first principal face (1m) and separated 3 mm or more from the outer edge thereof has an off-inclination angle ?? of ?10° or more, 10° or less with respect to the plane orientation of an arbitrarily designated crystalline plane (1a) that is inclined 50° or more, 90° or less with respect to a plane (1c), being either the (0001) plane or the (000 1) plane, through the arbitrary point. In this way a method of storing GaN substrates whose principal-face plane orientation is other than (0001) or (000 1), with which semiconductor devices of favorable properties can be manufactured is made available.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 2, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Publication number: 20130099277
    Abstract: A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N.
    Type: Application
    Filed: October 25, 2012
    Publication date: April 25, 2013
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: The Regents of the University of California
  • Patent number: 8420543
    Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 16, 2013
    Assignee: National Chiao Tung University
    Inventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
  • Patent number: 8383498
    Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 26, 2013
    Assignee: IMEC
    Inventor: Simone Severi
  • Patent number: 8283254
    Abstract: There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF4 gas, a COS gas and an O2 gas into a processing chamber and etching the antireflection coating layer by the etching gas while using the resist film as a mask.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Takahito Mukawa
  • Patent number: 8227826
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Publication number: 20120184102
    Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.
    Type: Application
    Filed: May 18, 2011
    Publication date: July 19, 2012
    Applicant: National Chiao Tung University
    Inventors: Wei-I Lee, Kuei-Ming Chen, Yin-Hao Wu, Yen-Hsien Yeh
  • Patent number: 8193099
    Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise, Hongwen Yan
  • Patent number: 8183669
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 22, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 8143168
    Abstract: The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Shigeharu Monoe
  • Publication number: 20120058644
    Abstract: A liquid composition free from N-alkylpyrrolidones and hydroxyl amine and its derivatives, having a dynamic shear viscosity at 50° C. of from 1 to 10 mPas as measured by rotational viscometry and comprising based on the complete weight of the composition, (A) of from 40 to 99.95% by weight of a polar organic solvent exhibiting in the presence of dissolved tetramethylammonium hydroxide (B) a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) of from 0.05 to <0.5% of a quaternary ammonium hydroxide, and (C) <5% by weight of water; method for its preparation, a method for manufacturing electrical devices and its use for removing negative-tone and positive-tone photoresists and post etch residues in the manufacture of 3D Stacked Integrated Circuits and 3D Wafer Level Packagings by way of patterning Through Silicon Vias and/or by plating and bumping.
    Type: Application
    Filed: April 20, 2010
    Publication date: March 8, 2012
    Applicant: BASF SE
    Inventor: Andreas Klipp
  • Patent number: 8114698
    Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: February 14, 2012
    Assignee: The Regents of the University of California
    Inventors: Hong Zhong, Anurag Tyagi, Kenneth J. Vampola, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 7981804
    Abstract: A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: July 19, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Michihiro Murata
  • Patent number: 7981805
    Abstract: The present invention provides a method for manufacturing a resistance change element that can reduce occurrence of corrosion without increasing a substrate temperature. A laminate film that includes a high melting-point metal film and a metal oxide film, is etched using a mask under a plasma atmosphere formed using any one of a mixture gas formed by adding at least one gas selected from the group consisting of Ar, He, Xe, Ne, Kr, O2, O3, N2, H2O, N2O, NO2, CO and CO2 to at least one kind of gasified compound selected from alcohol and hydrocarbon or the gas compound.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: July 19, 2011
    Assignee: Canon Anelva Corporation
    Inventors: Yoshimitsu Kodaira, Tomoaki Osada, Sanjay Shinde
  • Patent number: 7960284
    Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: June 14, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura
  • Patent number: 7935641
    Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Yeon-hee Kim, Jung-hyun Lee, Yong-young Park, Chang-soo Lee
  • Patent number: 7898038
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: March 1, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Patent number: 7872331
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 7851248
    Abstract: A capping technology is provided in which, despite the fact that structures which are surrounded by a silicon-germanium filling layer are exposed using ClF3 etching through micropores in the silicon cap, an etching attack on the silicon cap is prevented, namely, either by particularly selective (approximately 10,000:1 or higher) adjustment of the etching process itself, or by using the finding that the oxide of a germanium-rich layer, in contrast to oxidized porous silicon, is not stable but instead may be easily dissolved, to protect the silicon cap.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Silvia Kronmueller, Tino Fuchs, Ando Feyh, Christina Leinenbach, Marco Lammer
  • Patent number: 7838429
    Abstract: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: November 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Phan, Kyle M. Flessner, Martin B. Mollat, Connie Wang, Arthur Pan, Eric William Beach, Michelle R. Keramidas, Karen Elizabeth Burks
  • Patent number: 7820553
    Abstract: Methods of preventing photoresist scum formation for etch processes for patterning material layers of semiconductor device material layers are disclosed. A treatment of N2 and O2 is used to prevent the formation of photoresist scum. The treatment may be performed in-situ, and may be performed during the etch process, after the etch process, or both. The treatment is particularly beneficial when implemented during the patterning of low dielectric constant material layers, and when used for the formation of isolated via patterns.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: October 26, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Shen Chu, Chia-Piao Lee
  • Patent number: 7816265
    Abstract: A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 19, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Jen Wang
  • Patent number: 7811908
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: October 12, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 7544611
    Abstract: An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas).
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: June 9, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeo Shirahama
  • Patent number: 7534727
    Abstract: A predetermined pattern containing a plurality of gate patterns, in the process of formation thereof, is classified into fine gate patterns and the other patterns (S102), and a hard mask film is formed on a process target film (S106). Next, a first resist film having a fine first pattern is formed on the hard mask film, and the hard mask film is then patterned (S108). Thereafter, a resist film having a separate pattern is formed on the hard mask film, and a process target film is selectively dry-etched through the hard mask film and the resist film used as masks (S110 and S112).
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: May 19, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 7488667
    Abstract: A principal surface at one side of a support substrate has thereon an adjustment layer made of material having a higher thermal expansion coefficient than that of the support substrate. Then, a nitride-base semiconductor element layer and the support substrate on a growth substrate are joined via an adhesion layer. Next, the support substrate is joined to the nitride-base semiconductor element layer via the adhesion layer. Next, the growth substrate is separated from the joined nitride-base semiconductor element layer and the support substrate.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 10, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kunio Takeuchi, Yasumitsu Kunoh
  • Patent number: 7462566
    Abstract: In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: December 9, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Masato Fujita, Kensuke Taniguchi, Akira Mitsuiki
  • Publication number: 20080286976
    Abstract: A method of removing a metal suicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Application
    Filed: June 13, 2008
    Publication date: November 20, 2008
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu
  • Patent number: 7452823
    Abstract: An etching method, for selectively etching a silicon nitride film to a silicon oxide film by using a processing gas in a processing chamber including an electrode therein, includes the steps of mounting a target object having the silicon oxide film and the silicon nitride film onto the electrode and etching the silicon nitride film by introducing a gaseous mixture containing CF4 gas, H2 gas and N2 gas as a processing gas into the processing chamber and applying a high frequency power of 0.20 W/cm2 or less to the electrode while maintaining a pressure in the processing chamber to be equal to or smaller than 4 Pa.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: November 18, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Manabu Sato
  • Patent number: 7435691
    Abstract: A micromechanical component having a silicon substrate; a cavity provided in the substrate; and a diaphragm, provided on the surface of the substrate, which closes the cavity; the diaphragm featuring a silicon-oxide layer having an opening that is formed by silicon-oxide wedges pointing to each other; and the diaphragm having at least one closing layer which closes the opening. Also, a suitable manufacturing method.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: October 14, 2008
    Assignee: Robert Bosch GmbH
    Inventor: Heribert Weber
  • Patent number: 7432532
    Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Abhay A. Watwe, Sairam Agraharam, Kramadhati V Ravi, Michael C. Garner
  • Patent number: 7399708
    Abstract: Methods are provided for cleaning a microelectronic device, and one method includes providing a substrate having a patterned SOG/anti-reflective material; performing a process to cure the patterned SOG/anti-reflective material; and performing a cleaning process to remove the cured SOG/anti-reflective material. An apparatus for cleaning a microelectronic device is provided that includes a processing chamber; means for performing a SOG/anti-reflective material curing process within the processing chamber, means for performing a cleaning process within the processing chamber and means for venting the processing chamber.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: July 15, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Paul Schilling
  • Patent number: 7378351
    Abstract: A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: May 27, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Zempei Kawazu, Yuji Abe
  • Patent number: 7358110
    Abstract: An image sensor includes an inner lens to enable incident light to reach a condensing lens, so that the incident light may further reach photodiodes. Light loss can be reduced and photosensitivity can be improved. The image sensor includes at least one microlens that focuses incident light onto at least one photosensor that receives a light signal transmitted from the at least one microlens. The image sensor also includes at least one inner lens, disposed between the at least one microlens and the at least one photosensor, having an upper surface of a predetermined curvature to compensate photosensitivity of light received from the at least one microlens.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 15, 2008
    Assignee: Dongbu Electronics Co., Ltd
    Inventor: Sang Sik Kim
  • Publication number: 20070202704
    Abstract: A method for etching platinum (Pt) includes etching a platinum layer using a gas mixture including a fluorine (F) containing gas and an inert gas. A method for fabricating a capacitor having a bottom electrode, a dielectric layer, and an upper electrode includes forming the bottom electrode by etching a platinum layer, and forming the upper electrode by etching another platinum layer, wherein the platinum layers are etched using a gas mixture including a fluorine (F) containing gas and an inert gas.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 30, 2007
    Inventors: Su-Bum Shin, Hyun Ahn, Jung-Taik Cheong
  • Patent number: 7176534
    Abstract: The present invention provides a method for fabricating low-resistance, sub-0.1 ?m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Hussein I. Hanafi, Wesley Natzle