Abstract: An alkaline etching solution comprising a hydroxide salt (e.g., an alkali metal hydroxide, an ammonium hydroxide, or a combination thereof), a polyol having at least three hydroxyl (—OH) groups, and water. Also provided is a method of producing a semiconductor device by obtaining a semiconductor substrate having masked and unmasked surfaces; exposing the semiconductor substrate having the masked and unmasked surfaces to an alkaline etching solution, such that the unmasked surfaces of the substrate are anisotropically etched, wherein the alkaline etching solution comprises: a hydroxide salt; a polyol having at least three hydroxyl (—OH) groups; and water; and performing additional processing to produce the semiconductor device.

Abstract: Easy and accurate mating of a groove interval of a groove pattern of a diffraction grating with a position on a convex fixing substrate is enabled. For this purpose, a concave diffraction grating is fabricated by: transferring a groove pattern formed on a plane diffraction grating and having unequal groove intervals onto a metal thin film; forming a first alignment mark on a convex surface of a fixing substrate having the convex surface to fix the metal thin film; mating a second alignment mark formed on an adhesive surface of the metal thin film with the first alignment mark to perform alignment; bonding the adhesive surface of the metal thin film and the convex surface of the fixing substrate to each other to fabricate a master; and transferring a groove pattern of a metal thin film of the master.

Abstract: A method of forming a photonic device includes forming a cavity extending from a first major surface of a semiconductor wafer, performing a laser grooving process to form a first groove and a second groove, dicing the semiconductor wafer along the first groove and the second groove, and attaching an optical interposer to the bottom surface of the cavity. The cavity includes a first sidewall, an opposite second sidewall, and a bottom surface. The first groove is separated from the second groove by the cavity. The dicing passes through the cavity along a line connecting the first groove to the second groove.

Abstract: Printheads for a jetting apparatus. In one embodiment, a printhead comprises a plurality of nozzles configured to eject a print fluid. Each nozzle is comprised of a first converging section having a cross-sectional area that decreases in a flow direction of the print fluid through the nozzle, a neck adjoining the first converging section and having a cross-sectional area that is uniform in the flow direction of the print fluid through the nozzle, and a second converging section adjoining the neck and having a cross-sectional area that decreases in the flow direction of the print fluid through the nozzle.

Abstract: A hybrid diffraction grating, a mold used to produce the hybrid diffraction grating, and their manufacturing methods are described. In one aspect, a hybrid diffraction grating comprises a grating main body and a reflective layer. The grating main body comprises numerous diffraction structures. When viewed along a top-view direction, the numerous diffraction structures are arranged in a pattern defined by a profile. The profile determines various blaze angles of the numerous diffraction structures. The reflective layer, disposed on the diffraction structures, exhibits characteristics of the numerous diffraction structures.

Abstract: A photovoltaic modular connector system is disclosed. Electrically conductive contacts embedded into the surface of each of one or more photovoltaic (PV) modules provide the connection point for two PV modules to be connected together. PV modules are connected together by removing a protective backing material from an adhesive area surrounding a first set of contacts of a first PV module, and adhering to an adhesive area surrounding a second set of contacts of a second PV module, the adhesive making the connection and sealing and protecting the contact area. No external wiring, connectors or devices are required to make the electrical connection between two PV modules. Contacts are integral and embedded into the surface of each individual PV module. The PV modules have adhesive on the back to allow them to be adhesively attached to a surface without additional mounting hardware.

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

Abstract: A manufacturing method of a Blazed diffraction grating configured to diffract incident light and made of a CdTe or CdZnTe crystal material includes the step of forming a plurality of grating grooves in a processed surface of a work through machining using a processing machine for the Blazed diffraction grating. The forming step forms the grating grooves so that among surfaces of gratings formed by the forming step, a surface that receives the incident light most is set to a (110) plane as a crystal orientation of the crystal material.

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.

Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.

Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.

Abstract: A method for manufacturing a liquid discharge includes a process of forming a plurality of blind holes extending from a first surface of the silicon substrate toward a second surface which is a surface opposite to the first surface in the silicon substrate and a process of subjecting the silicon substrate in which the plurality of blind holes are formed to anisotropic etching from the first surface to form a liquid supply port in the silicon substrate, in which, in the process of forming the liquid supply port, the silicon in a region sandwiched by the plurality of blind holes when the silicon substrate is seen from the second surface side is left without being removed by the anisotropic etching to use the left silicon as a beam.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.

Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

Abstract: A method of fabricating a three-dimensional semiconductor device includes forming a stacked structure, and the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. The method also includes forming a sacrificial spacer on a sidewall of the stacked structure such that the sacrificial spacer exposes a sidewall of the third layer, and recessing the exposed sidewall of the third layer thereby forming a recess region between the second and fourth layers.

Abstract: In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etching liquid having a long life of etching liquid and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etching liquid. A silicon etching liquid which is an alkaline aqueous solution containing an alkali metal hydroxide, hydroxylamine and an inorganic carbonate compound and having a pH of 12 or more and which is able to anisotropically dissolve monocrystalline silicon therein, and an etching method of silicon using this etching liquid are provided.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

Abstract: The present invention relates to a method of treating wafers comprising at least one surface layer of silicon-germanium (SiGe) and a layer of strained silicon (sSi) in contact with the SiGe layer, the sSi layer being exposed by etching of the SiGe layer, the method comprising the steps of: (a) a first selective etch of the SiGe layer, optionally followed by an oxidative cleaning step; (b) a rinsing step using deionized water; (c) drying; and (d) a second selective etch step. The present invention relates to a wafer comprising at least one surface layer of strained silicon (sSi), the at least one surface layer of sSi having a thickness of at least 5 nm and at most 100 ?m and having at most 200 defects per wafer.

Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: A method of manufacturing an electronic device includes: preparing a film-attached substrate including a substrate, and an oxide semiconductor film containing In, Ga, and Zn and a metal film containing at least one of W or Mo provided in this order on the substrate; and wet-etching the metal film of the film-attached substrate using an etching liquid of which a main component is hydrogen peroxide under conditions such that an etching selection ratio between the metal film and the oxide semiconductor film (etching rate of the metal film/etching rate of the oxide semiconductor film) is 100 or higher.

Abstract: An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or derivative thereof. Also provided is a process for texture etching a silicon wafer using the etching liquid of the invention.

Abstract: A method of forming micro-pore structures or trench structures on a surface of a silicon wafer substrate comprises (A) forming at least a noble-metal alloy particle on the surface of the silicon wafer substrate; and (B) then followed by employing a chemical wet etching on the surface of the silicon wafer substrate. During the processes, noble-metal alloy particle is used to catalyze the oxidation of the silicon wafer substrate surface in contact therewith, and an etchant is used to simultaneous etch the silicon dioxide to result in local micro-etching at the surface of the silicon wafer substrate, thereby forming micro-pore structures or trench structures on the surface of the silicon wafer substrate. The method increases the power conversion efficiency of the solar cells and reduces the manufacturing costs so as to increase the production benefits of the solar cells.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the channel region of the semiconductor device. The semiconductor device further includes first and second trenches formed adjacent to the gate stack, where the first and second trenches are conically shaped to be wider at a top portion of each trench as compared to a width of each trench below the top portion of each trench. The semiconductor device further includes strained silicon alloy formed within the first and second trenches, where a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.

Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.

Abstract: A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second side to form a cavity in corresponding to the diaphragm and a plurality of venting holes in the substrate. An isotropic etching process is performed from the first side and the second side of the substrate via vent holes to remove a dielectric portion of the structural dielectric layer for exposing a central portion of the diaphragm while an end portion is held by a residue portion of the structural dielectric layer.

Abstract: An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.

Abstract: A substrate processing method including the steps of disposing a substrate having a recess in such a manner that the face having the recess is upward in the gravity direction, and applying a resist to the recess and face having the recess to form a resist film thereon, and disposing the substrate having the resist film formed thereon in such a manner that the face having the recess is downward in the gravity direction, and applying a liquid capable of dissolving the resist to the resist film to adjust the thickness of the resist film. A method for manufacturing a liquid ejection head is also provided.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: A process for etching a silicon layer disposed on a substrate, including anisotropically etching a first trench in the silicon layer; selectively anisotropic wet etching silicon surfaces in the first trench, the wet etching comprising exposing the silicon surfaces to an aqueous composition including an aromatic tri(lower)alkyl quaternary onium hydroxide, and an unsymmetrical tetraalkyl quaternary phosphonium salt; in which the wet etching etches (110) and (100) planes of the silicon layer at about equal rates and preferentially to the (111) plane to form an enlarged trench having a sidewall in the (111) plane. A silicon alloy may be epitaxially deposited in the thus-produced trench as part of a process of introducing stress into at least a portion of the silicon layer.

Abstract: The microelectronic device interconnects are fabricated by a process that utilizes a silicon-based interlayer dielectric material layer, such as carbon-doped oxide, and a chemical mixture selective to materials used in the formation of the interconnects, including, but not limited to, copper, cobalt, tantalum, and/or tantalum nitride, to remove the interlayer dielectric material layer between adjacent interconnects thereby forming air gaps therebetween.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: A nitriding process is performed at a process temperature of 500° C. or more by causing microwave-excited high-density plasma of a nitrogen-containing gas to act on silicon in the surface of a target object, inside a process container of a plasma processing apparatus. The plasma is generated by supplying microwaves into the process container from a planar antenna having a plurality of slots.

Abstract: Semiconductor substrates are cleaned and subsequently oxidized. After the semiconductor is oxidized it is textured to reduce incident light reflectance. The textured semiconductors can be used in the manufacture of photovoltaic devices.

Abstract: Method of manufacturing semiconductor device including forming inter-layer insulating film on semiconductor substrate. First metal film is formed on inter-layer insulating film. First resist is formed on first metal film and patterned. Anisotropic etching performed on first metal film using first resist as mask. First resist is removed and second metal film is formed on inter-layer insulating film to cover remaining first metal film. Second resist is formed on second metal film in area where first metal film exists on inter-layer insulating film and part of area where first metal film does not exist. Anisotropic etching is performed on second metal film using second resist as mask and bonding pad having first metal film and second metal film, and upper layer wiring having second metal film and not first metal film. Second resist is removed. Surface protection film covering bonding pad is formed. Pad opening is formed on bonding pad.

Abstract: A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region.

Abstract: A photoresist composition includes a binder resin, a photo acid generator, an acryl resin having four different types of monomers, and a solvent.

Abstract: In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etching liquid having a long life of etching liquid and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etching liquid. A silicon etching liquid which is an alkaline aqueous solution containing an alkali metal hydroxide, hydroxylamine and an inorganic carbonate compound and having a pH of 12 or more and which is able to anisotropically dissolve monocrystalline silicon therein, and an etching method of silicon using this etching liquid are provided.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.