Post-treatment (epo) Patents (Class 257/E21.241)
  • Patent number: 10411221
    Abstract: Provided is an organic electronic device comprising: a substrate on which an organic photoelectric device unit is arranged; a first encapsulation film that encloses the organic photoelectric device unit and contains an inorganic or organic material; a second encapsulation film that encloses the first encapsulation film and contains a cured product of a photo-curable material having an ethylenically unsaturated bond; and a third encapsulation film that encloses the second encapsulation film and contains a photo-cured product of a photo-curable spin on glass (SOG) material.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 10, 2019
    Assignee: HUNET PLUS
    Inventors: Hyuk Jin Cha, Mi Sun Yoo
  • Patent number: 10262944
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Patent number: 10199388
    Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 5, 2019
    Assignee: APPLIED MATEERIALS, INC.
    Inventors: Michael Wenyoung Tsiang, Praket P. Jha, Xinhai Han, Bok Hoen Kim, Sang Hyuk Kim, Myung Hun Ju, Hyung Jin Park, Ryeun Kwan Kim, Jin Chul Son, Saiprasanna Gnanavelu, Mayur G. Kulkarni, Sanjeev Baluja, Majid K. Shahreza, Jason K. Foster
  • Patent number: 10079153
    Abstract: In a substrate processing method according to the embodiment, a first material is implanted into a surface of a target film to modify the surface of the target film. The surface of the target film is dissolved to remove the surface of the target film by bringing a catalytic material close to the surface of the target film or by contacting the catalytic material to the surface of the target film while supplying a process solution on the surface of the target film which has been modified.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: September 18, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki
  • Patent number: 10070005
    Abstract: An identification document holding system and method can include: an outer cover having: a hinge, a top flap having a top flap inner portion in direct contact with the hinge and a top flap body extending away from the top flap inner portion and the top flap body terminating in a top flap outer side, and a bottom flap having a bottom flap inner portion in direct contact with the hinge and a bottom flap body extending away from the bottom flap inner portion and the bottom flap body terminating in a bottom flap outer side; a top pocket with a top pocket opening near the hinge and the top pocket configured to hold pages of the identification document; a bottom pocket with a bottom pocket opening at a distance larger than the distance between the top pocket opening and the hinge, the bottom pocket configured to hold a bottom end of an identification document and leave identification information on the identification document fully readable and exposed therefrom; and wherein the identification document holding syst
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 4, 2018
    Inventor: Sonali Deshpande
  • Patent number: 10032879
    Abstract: A thin film transistor (TFT) substrate includes an insulating layer, an electrode on the insulating layer, and a main buffering layer connecting a side surface of the electrode to an upper surface of the insulating layer.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyuneok Shin
  • Patent number: 9950464
    Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound is disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Myung Jin Yim, Jason M. Brand
  • Patent number: 9748360
    Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. In a manufacturing method of a semiconductor device according to an embodiment, when a resist pattern is formed over a cap insulating film comprising a silicon nitride film, the resist pattern is formed through the processes of coating, exposure, and development treatment of a chemical amplification type resist. Then the chemical amplification type resist is applied so as to directly touch the surface of the cap insulating film comprising the silicon nitride film and organic acid pretreatment is applied to the surface of the cap insulating film comprising the silicon nitride film before the coating of the chemical amplification type resist.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 29, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya Hagiwara, Tetsuro Hanawa
  • Patent number: 9673039
    Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Yiqun Liu, Jin Ping Liu, Fabio D'Addamio, Sandeep Gaan
  • Patent number: 9627512
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Mu-Tsang Lin
  • Patent number: 9620375
    Abstract: A production methods includes providing a substrate including a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle ? from at least a first or second main surface region of the substrate, the first and second main surface regions extending parallel to each other; anisotropic etching, starting from the first main surface region, into the substrate so as to obtain an etching structure which includes, in a plane extending perpendicularly to the first main surface region, two different etching angles relative to the first main surface region; arranging a cover layer on the first main surface region, so that the cover layer lies against the etching structure in at least some sections; and removing, section-by-section, the material of the substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 11, 2017
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Sergiu Langa, Christian Drabe, Thilo Sandner
  • Patent number: 9583432
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 28, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Patent number: 9502239
    Abstract: There is provided a substrate processing method, including: (a) loading a substrate into a processing vessel having a pre-baked film containing a silazane bond; (b) heating the substrate to a first temperature and supplying a process gas to the heated substrate; and (c) heating the substrate to which the process gas has been supplied, to a second temperature which is higher than the first temperature and less than or equal to a temperature at which the pre-bake has been performed.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: November 22, 2016
    Assignees: HITACHI KOKUSAI ELECTRIC INC., AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.A.R.L.
    Inventors: Masahisa Okuno, Tooru Kakuda, Hideto Tateno, Takuya Joda, Masamichi Kurokawa
  • Patent number: 9486945
    Abstract: The present invention concerns a method and a device for curing a thermosetting polymer. The method comprises the steps of irradiating the thermosetting polymer with microwaves at a first power level so as to heat up the thermosetting polymer by dielectric heating, and when the thermosetting polymer reaches a first predetermined temperature, irradiating the thermosetting polymer with microwaves at a second power level, substantially higher than the first power level, to further heat up the thermosetting polymer by dielectric heating. The device comprises an enclosure for receiving the thermosetting polymer, a microwave emitter for emitting microwave radiation into the enclosure, and a control unit for controlling a microwave emission power of the microwave emitter according to the abovementioned method.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 8, 2016
    Assignee: TOYOTA MOTOR EUROPE NV/SA
    Inventors: Yasuhiro Akita, Andrew Willett
  • Patent number: 9460997
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9401302
    Abstract: An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a first annealing process, the first annealing process including a first wet anneal, a second wet anneal, and a first dry anneal. In an embodiment, the first annealing process is followed by a chemical mechanical planarization (CMP) process, an etching process, and a second annealing process for the isolation region.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Shiang-Rung Tsai
  • Patent number: 9390908
    Abstract: The invention provides a method for manufacturing a barrier layer on a substrate, the method comprising: providing a substrate with an inorganic oxide layer having a pore volume between 0.3 and 10 vol. %; treating said substrate with an inorganic oxide layer in a glow discharge plasma, said plasma being generated by at least two electrodes in a treatment space formed between said two electrodes, said treatment space also being provided with a gas comprising Nitrogen compounds; and the treating of the substrate in said treatment space is done at a temperature below 150° C., e.g. below 100° C. The invention further provides a device for manufacturing a barrier layer on a substrate.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 12, 2016
    Assignee: Fujifilm Manufacturing Europe BV
    Inventors: Serguei Starostine, Hindrik De Vries
  • Patent number: 9177785
    Abstract: A method of forming a semiconductor structure is provided. The method comprises mixing a water soluble substance with an aprotic solvent to form a solvent mixture and forming a thin layer of oxide around a semiconductor surface by performing wet chemical oxidation operations on the semiconductor surface with the solvent mixture. The aprotic solvent may comprise propylene carbonate, dimethyl sulfoxide, ethylene carbonate or diethyl carbonate. The water soluble substance may comprise H2O2, O3, or parts per million (ppm) level H2O. The method may further comprise removing the oxide from the semiconductor surface to reduce the roughness of the semiconductor surface. The method may further comprise forming a second thin layer of oxide around the semiconductor surface by performing wet chemical oxidation operations with the solvent mixture and removing the second layer of oxide from the semiconductor surface to smoothen the semiconductor surface.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Andrew Joseph Kelly, Yusuke Oniki
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 9018089
    Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eric G. Liniger, Griselda Bonilla, Pak Leung, Stephen A. Cohen, Stephen M. Gates, Thomas M. Shaw
  • Patent number: 8907451
    Abstract: A semiconductor chip includes a semiconductor substrate having one and the other surfaces and formed with a plurality of semiconductor devices; an internal wiring layer having multi-layered internal wiring lines which are formed over the one surface and are electrically connected with the plurality of semiconductor devices, an uppermost internal wiring line among the internal wiring lines being formed with a power supply pad and a ground pad; a dielectric layer formed over the uppermost internal wiring line in such a way as to expose the power supply pad and the ground pad; an external connection reinforcing line formed over the power supply pad or the ground pad which is exposed, and extending onto the dielectric layer; and an embedded capacitor constituted by the external connection reinforcing line, and the dielectric layer and a portion of the uppermost internal wiring line which correspond to the external connection reinforcing line.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 8877628
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technologies, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Patent number: 8716148
    Abstract: A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiyuki Ohkura, Toshiki Mori
  • Publication number: 20140065838
    Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A second inorganic thin film dielectric material layer is deposited on the treated surface of the first inorganic thin film dielectric material layer using an atomic layer deposition process.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
  • Publication number: 20140015143
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 8629508
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Publication number: 20130252425
    Abstract: A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Han LIN, Ming-Ching CHANG, Ryan Chia-Jen CHEN, Yih-Ann LIN, Jr-Jung LIN
  • Patent number: 8525166
    Abstract: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8507390
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 13, 2013
    Assignee: Sandisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8502286
    Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park
  • Publication number: 20130196481
    Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")
    Inventors: Chia Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 8481429
    Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 9, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Heon Kim, Cheol Kyu Bok
  • Patent number: 8445377
    Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
  • Patent number: 8440578
    Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 14, 2013
    Assignee: TEL Epion Inc.
    Inventor: John Gumpher
  • Patent number: 8415252
    Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Abhishek Dube, Zhengwen Li, Huilong Zhu
  • Publication number: 20130078786
    Abstract: A film of silicon dioxide is formed on the silicon-germanium layer, and a high dielectric constant film is further formed on the film of silicon dioxide. First irradiation from a flash lamp is performed on the semiconductor wafer to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 3 milliseconds to 1 second. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 3 milliseconds to 1 second. This promotes the crystallization of the high dielectric constant film while suppressing the alleviation of distortion in the silicon-germanium layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 28, 2013
    Inventors: Kazuhiko FUSE, Shinichi KATO
  • Publication number: 20130075870
    Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 28, 2013
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: STMicoelectronics (Crolles 2) SAS, STMicroelectronics SA,
  • Publication number: 20130078820
    Abstract: In an imprint method of an embodiment, in the imprinting of an imprint shot including an outermost peripheral region of a substrate where resist is not desired to be entered at the time of imprinting, light curing the resist is applied to a light irradiation region with a predetermined width including a boundary between the outermost peripheral region and a pattern formation region more inside than the outermost peripheral region, whereby the resist which is to enter inside the outermost peripheral region is cured. Then, light curing the resist filled in a template pattern is applied onto a template.
    Type: Application
    Filed: March 15, 2012
    Publication date: March 28, 2013
    Inventor: Shinji MIKAMI
  • Publication number: 20130072018
    Abstract: Damaged surface areas of low-k dielectric materials may be efficiently repaired by avoiding the saturation of dangling silicon bonds after a reactive plasma treatment on the basis of OH groups, as is typically applied in conventional process strategies. The saturation of the dangling bond may be accomplished by directly initiating a chemical reaction with appropriate organic species, thereby providing superior reaction conditions, which in turn results in a more efficient restoration of the dielectric characteristics.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Matthias Schaller, Daniel Fischer, Thomas Oszinda
  • Publication number: 20130049104
    Abstract: A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Inventors: Sung-Shan Tai, Teng-hao Yeh, Chia-Hui Chen
  • Publication number: 20130048984
    Abstract: A method for patterning a multi-layer film in a semiconductor device is provided. The semiconductor device comprises a substrate and a multi-layer film on the substrate. The multi-layer film comprises N conductive layers and N dielectric layers alternatingly stacked, and 2N contact plugs. The Nth dielectric layer is formed at the top of the multi-layer film. The distances between the centers of each adjacent contact plugs are the same.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chin-Cheng Yang
  • Publication number: 20130043551
    Abstract: A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film, the first film having a first portion connected to the substrate, a second portion located above the sacrificial film, a third portion located between the first portion and the second portion, and a thin region in a portion of the third portion or in a boundary section between the second portion and the third portion and having a thickness smaller than the first portion; (c) removing the sacrificial film; and (d) bending the first film in the thin region, after the step (c), thereby sloping the second portion of the first film with respect to the substrate.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 21, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takahiko YOSHIZAWA
  • Publication number: 20130026610
    Abstract: Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Inventor: Durga Prasanna Panda
  • Publication number: 20130023124
    Abstract: Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Inventors: Srinivas D. Nemani, Yifeng Zhou, Dmitry Lubomirsky, Ellie Yieh
  • Patent number: 8354345
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Oh Lee
  • Publication number: 20130012031
    Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20120329285
    Abstract: A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shao-Wei WANG, Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8329552
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien