By Dry-etching (epo) Patents (Class 257/E21.256)
  • Patent number: 7495239
    Abstract: A cleaning arrangement for a lithographic apparatus module may be provided in a collector. The cleaning arrangement includes a hydrogen radical source configured to provide a hydrogen radical containing gas to at least part of the module and a pump configured to pump gas through the module such that a flow speed of the hydrogen radical containing gas provided through at least part of the module is at least 1 m/s. The cleaning arrangement may also include a gas shutter configured to modulate a flow of the hydrogen radical containing gas to at least part of the module, a buffer volume of at least 1 m3 in communication with the module, and a pump configured to provide a gas pressure in the buffer volume between 0.001 mbar (0.1 Pa) and 1 mbar (100 Pa).
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: February 24, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Johannes Maria Freriks, Vadim Yevgenyevich Banine, Vladimir Vitalevitch Ivanov
  • Publication number: 20080299760
    Abstract: A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating film is 100 or more, to an interlayer film for forming the contact plugs therein. The method comprises forming wiring lines each of which is covered with silicon oxide films at its top surface and lateral sides, forming a sacrificial interlayer film overall, which is made up of an organic coating film without containing silicon, so as to cover the wiring lines, forming contact holes by sequentially etching the sacrificial interlayer film and a lower-layer insulating film, and forming contact plugs.
    Type: Application
    Filed: February 26, 2008
    Publication date: December 4, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Atsushi MAEKAWA
  • Patent number: 7459363
    Abstract: A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge roughness (LER) of the masking structure, and etching a pattern of the layered masking structure into one or more of the number of layers of the substrate assembly before trimming the layered masking structure.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Krupakar M. Subramanian
  • Patent number: 7459391
    Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiko Yoshizawa, Noriaki Matsunaga, Naofumi Nakamura
  • Publication number: 20080286939
    Abstract: An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor substrate is selectively etched on the insulating layer side to a region at a greater depth than the embrittled layer; and the semiconductor substrate and a substrate having an insulating surface are superposed on each other and bonded to each other with the insulating layer interposed therebetween. The semiconductor substrate is heated to be separated at the embrittled layer while a semiconductor layer is left remaining over the substrate having an insulating surface.
    Type: Application
    Filed: March 28, 2008
    Publication date: November 20, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7435663
    Abstract: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such that the photoresist will protect the released structures free from the chipping, vibrations, and damages in the diamond blade dicing process. In another method, a laser dicing system is utilized to scribe the multi-project wafer placed on a platform, and by precisely controlling the platform moving-track, the dicing path can be programmed to any required shape and region, even it is not straight. In addition, the wafer backside is mounted on a blue-tape at the beginning to enhance the process reliability.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 14, 2008
    Assignee: National Applied Research Laboratories National Chip International Center
    Inventors: Sheng-Hsiang Tseng, Fu-Yuan Xiao, Ying-Zong Juang, Chin-Fong Chiu
  • Patent number: 7419902
    Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 2, 2008
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd
    Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
  • Patent number: 7416973
    Abstract: By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification of the etch behavior of the exposed portion of the contact etch stop layer.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 26, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Peters, Heike Salz, Ralf Richter, Matthias Schaller
  • Patent number: 7413963
    Abstract: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface of the wafer. Subsequently, the coating material layer positioned in the bevel region is removed according to the reference pattern.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: August 19, 2008
    Assignee: Touch Micro-System Technology Inc.
    Inventors: Shih-Min Huang, Sh-Pei Yang
  • Patent number: 7381622
    Abstract: By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: June 3, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andreas Hellmich, Gunter Grasshoff, Fernando Koch, Andy Wei, Thorsten Kammler
  • Patent number: 7344993
    Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving a hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluorocarbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. A chamber pressure less than 20 mTorr is utilized in the second cleaning step. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: March 18, 2008
    Assignee: Tokyo Electron Limited, Inc.
    Inventors: Vaidyanathan Balasubramaniam, Yasunori Hatamura, Masaaki Hagihara, Eiichi Nishimura, Rie Inazawa, legal representative, Koichiro Inazawa
  • Patent number: 7344927
    Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: March 18, 2008
    Assignee: Au Optronics Corporation
    Inventors: Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto
  • Patent number: 7341935
    Abstract: A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: March 11, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Yi-Chun Huang
  • Patent number: 7326653
    Abstract: A method for preparing an organic electronic or optoelectronic device is described. The method comprises depositing a layer of fluorinated polymer on a substrate, patterning the layer of fluorinated polymer to form a relief pattern and depositing from solution a layer of organic semiconductive or conductive material on the substrate. The fluorinated polymer may be a fluorinated photoresist and may be treated by exposure to ultraviolet light and ozone prior to the deposition of the layer of organic semiconductive or conductive material. The method has particular application in the preparation of organic light emitting devices by ink-jet printing.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: February 5, 2008
    Assignee: Cambridge Display Technology Limited
    Inventors: Alec Gunner, Martin Cacheiro
  • Patent number: 7276448
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Charles H Dennison, Trung T. Doan
  • Patent number: 7273817
    Abstract: A method is provided for forming polymer on an interior surface of a reaction chamber. A polymer-forming gas is introduced into the chamber during the etching of a photoresist layer of a semiconductor wafer within the reaction chamber and the environment is regulated to form the polymer on the interior surface of the chamber. The polymer thus formed reduces the standard deviation of the critical dimensions of the semiconductor wafer. A method for the manufacture of integrated circuits is also provided.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: William A. Polinsky, Bill Crane, John C. Gonzales, Steven Ott
  • Patent number: 7235479
    Abstract: A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist layer on the sacrificial material to define a trench for the semiconductor device, removing the first photoresist layer without affecting the sacrificial material, repatterning a second photoresist layer on the sacrificial material to define the trench for the semiconductor device, forming the trench, and removing the second photoresist layer and the sacrificial material completely after the trench is formed.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: June 26, 2007
    Assignee: Applied Materials, Inc.
    Inventor: Steven Verhaverbeke
  • Patent number: 7232763
    Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Makiko Katano, Shoko Ito, Takaya Matsushita, Hisashi Kaneko
  • Patent number: 7232768
    Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 19, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Mona M. Eissa
  • Patent number: 7208407
    Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Roger W. Lindsay, Frances May, Robert Veltrop
  • Patent number: 7179752
    Abstract: A dry etching method involves plasma etching an organic anti-reflecting coating film through a mask layer made of photoresist and having a predetermined pattern by using an etching gas of CF4 and O2. The method allows an organic anti-reflecting coating film to be etched such that the etched film exhibits a side wall portion having a better shape as compared with that formed by a conventional technique.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: February 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Akitaka Shimizu, Takashi Tsuruta, Takashi Enomoto, Hiromi Oka, Akiteru Koh
  • Patent number: 7179751
    Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: February 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Mona M. Eissa