Organic Layers, E.g., Photoresist (epo) Patents (Class 257/E21.259)
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Publication number: 20120129353Abstract: Provided by the present invention is a method including: (1) forming a resist underlayer film on the upper face side of a substrate to be processed using a composition for forming a resist underlayer film, the composition containing (A) a compound having a group represented by the following formula (1); (2) forming a resist coating film by applying a resist composition on the resist underlayer film; (3) exposing the resist coating film by selectively irradiating the resist coating film with a radiation; (4) forming a resist pattern by developing the exposed resist coating film; and (5) forming a predetermined pattern on the substrate to be processed by sequentially dry etching the resist underlayer film and the substrate using the resist pattern as a mask.Type: ApplicationFiled: September 28, 2011Publication date: May 24, 2012Applicant: JSR CorporationInventors: Shin-ya MINEGISHI, Shin-ya Nakafuji, Satoru Murakami, Toru Kimura
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Publication number: 20120126372Abstract: A resist pattern thickening material is disclosed that can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. Also disclosed is a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: FUJITSU LIMITEDInventors: Miwa Kozawa, Koji Nozaki
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Publication number: 20120115331Abstract: Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.Type: ApplicationFiled: November 1, 2011Publication date: May 10, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-won Koh, Min-joon Park, Chang-Min Park
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Publication number: 20120115333Abstract: A polybenzoxazole precursor is represented by the following formula (1): wherein R1a to R4a, R1b to R4b, X1, Y1 and m are defined in the specification.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Applicant: FUJIFILM CORPORATIONInventors: Kenichiro SATO, Tsukasa YAMANAKA
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Publication number: 20120108071Abstract: There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, namely, an underlayer film having optimum n-value and k-value, excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.Type: ApplicationFiled: October 7, 2011Publication date: May 3, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Tsutomu OGIHARA, Daisuke KORI, Yusuke BIYAJIMA, Toshihiko FUJII, Takeru WATANABE, Takeshi KINSHO
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Publication number: 20120098147Abstract: A method for manufacturing a semiconductor device having fluorocarbon layers as insulating layers includes the steps of forming a first fluorocarbon (CFx1) layer using plasma excited by microwave power and forming a second fluorocarbon (CFx2) layer using plasma excited by an RF power.Type: ApplicationFiled: June 25, 2010Publication date: April 26, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Hiroyuki Takaba
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Publication number: 20120100725Abstract: A method of forming an amorphous carbon layer on an insulating layer includes the step of forming an amorphous carbon layer using a plasma reaction process. The amorphous carbon layer is formed in an atmosphere containing a plasma excitation gas, a CxHy series gas, a silicon-containing gas, and an oxygen-containing gas.Type: ApplicationFiled: June 25, 2010Publication date: April 26, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Yoshiyuki Kikuchi
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Patent number: 8148805Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2011Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
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Publication number: 20120070994Abstract: There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hard mask; and a forming method of a resist pattern using the underlayer film forming composition for lithography. A resist underlayer film forming composition for lithography comprising: as a silicon atom-containing compound, a hydrolyzable organosilane containing a sulfur atom-containing group, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein in the whole silicon atom-containing compound, the ratio of a sulfur atom to a silicon atom is less than 5% by mole. The hydrolyzable organosilane is preferably a compound of Formula (1): [R1aSi(R2)3-a]bR3 wherein R3 has a partial structure of Formula (2): R4—S—R5.Type: ApplicationFiled: May 28, 2010Publication date: March 22, 2012Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Yuta Kanno, Makoto Nakajima, Wataru Shibayama
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Publication number: 20120037871Abstract: The invention relates to compounds comprising a cycloalkyne or heterocycloalkyne group and a redox group. Said compounds are of general formula (I) wherein Z is a cycloalkyne or heterocycloalkyne with at least 8 links, optionally substituted by a halogen atom or a linear or branched C1 to C5 alkyl, A is an organic structure having oxidation-reduction properties, and B is an organic link between the cycloalkyne or heterocycloalkyne cycle and the organic structure A. The invention is especially applicable to the field of molecular electronics.Type: ApplicationFiled: March 16, 2010Publication date: February 16, 2012Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Guillaume Delapierre, Regis Barattin, Aude Bernardin, Isabelle Texier-Nogues
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Publication number: 20120032306Abstract: A method for patterning a semiconductor surface is specified. A photoresist is applied to an outer area of a second semiconductor wafer. A surface of the photoresist that is remote from the second semiconductor wafer is patterned by impressing a patterned surface of the first wafer into the photoresist. A patterning method is applied to the surface of the photoresist, wherein a structure applied on the photoresist is transferred at least in places to the outer area of the second semiconductor wafer.Type: ApplicationFiled: January 22, 2010Publication date: February 9, 2012Applicant: OSRAM Opto Semiconductors GmbHInventors: Elmar Baur, Bernd Böhm, Alexander Heindl, Patrick Rode, Matthias Sabathil
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Patent number: 8110432Abstract: Thin film transistor substrates with conductor components in conjunction therewith, and related methods of fabrication.Type: GrantFiled: August 13, 2007Date of Patent: February 7, 2012Assignee: Northwestern UniversityInventors: Tobin J. Marks, Antonio Facchetti
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Publication number: 20120028471Abstract: A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.Type: ApplicationFiled: February 18, 2011Publication date: February 2, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Kenichi Oyama, Kazuo Yabe, Hidetami Yaegashi
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Publication number: 20120028476Abstract: Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes forming a set of shapes on top of a substrate; applying a layer of copolymer covering the substrate; causing the copolymer to form a plurality of cylindrical blocks both inside and outside the shapes; forming a pattern of contact holes from the plurality of cylindrical blocks; and transferring the pattern of contact holes to the substrate to form the semiconductor structure. In one embodiment, the shapes are rings and forming the set of shapes includes forming a set of rings that are equally and squarely spaced. In another embodiment, causing the copolymer to form the plurality of cylindrical blocks includes forming only one cylindrical block inside each of the rings and only one cylindrical block outside every four (4) squarely neighboring rings.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wai-Kin Li, Wu-Song Huang, Joy Cheng, Kuang-Jung Chen
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Publication number: 20120028477Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.Type: ApplicationFiled: October 7, 2011Publication date: February 2, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Clement Hsingjen Wann, Ching-Yu Chang
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Publication number: 20120015527Abstract: For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures.Type: ApplicationFiled: September 22, 2011Publication date: January 19, 2012Inventors: SHI-YONG Yi, KYOUNG-TAEK KIM, HYUN-WOO KIM, DONG-KI YOON
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Publication number: 20120009524Abstract: A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer.Type: ApplicationFiled: September 21, 2011Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Wei Yeh, Jen-Chieh Shih, Jian-Hong Chen
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Publication number: 20120009413Abstract: Densifying a multi-layer substrate includes providing a substrate with a first dielectric layer on a surface of the substrate. The first dielectric layer includes a multiplicity of pores. Water is introduced into the pores of the first dielectric layer to form a water-containing dielectric layer. A second dielectric layer is provided on the surface of the water-containing first dielectric layer. The first and second dielectric layers are annealed at temperature of 600° C. or less. In an example, the multi-layer substrate is a nanoimprint lithography template. The second dielectric layer may have a density and therefore an etch rate similar to that of thermal oxide, yet may still be porous enough to allow more rapid diffusion of helium than a thermal oxide layer.Type: ApplicationFiled: July 7, 2011Publication date: January 12, 2012Applicant: MOLECULAR IMPRINTS, INC.Inventors: Marlon Menezes, Frank Y. Xu, Fen Wan
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Publication number: 20110309511Abstract: Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.Type: ApplicationFiled: August 31, 2011Publication date: December 22, 2011Applicant: Elpida Memory, Inc.Inventors: Yoshinori CHO, Takamaro Kikkawa
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Publication number: 20110300712Abstract: Methods of forming a photoresist pattern include forming a first photoresist pattern on a substrate and treating the first photoresist pattern with plasma that modifies etching characteristics of the first photoresist pattern. This modification may include making the first photoresist pattern more susceptible to removal during subsequent processing. The plasma-treated first photoresist pattern is covered with a second photoresist layer, which is patterned into a second photoresist pattern that contacts sidewalls of the plasma-treated first photoresist pattern. The plasma-treated first photoresist pattern is selectively removed from the substrate to reveal the remaining second photoresist pattern. The second photoresist pattern is used as an etching mask during the selective etching of a portion of the substrate (e.g., target layer).Type: ApplicationFiled: May 9, 2011Publication date: December 8, 2011Inventors: Kyoung-Mi Kim, Jeong-Ju Park, Mi-Ra Park, Bo-Hee Lee, Jae-Ho Kim, Young-Ho Kim
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Publication number: 20110291204Abstract: A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.Type: ApplicationFiled: August 15, 2011Publication date: December 1, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yoshiyuki Ookura
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Publication number: 20110287633Abstract: A method of forming an amorphous carbon layer on a substrate in a substrate processing chamber, includes introducing a hydrocarbon source into the processing chamber, introducing argon, alone or in combination with helium, hydrogen, nitrogen, and combinations thereof, into the processing chamber, wherein the argon has a volumetric flow rate to hydrocarbon source volumetric flow rate ratio of about 10:1 to about 20:1, generating a plasma in the processing chamber at a substantially lower pressure of about 2 Torr to 10 Torr, and forming a conformal amorphous carbon layer on the substrate.Type: ApplicationFiled: May 20, 2010Publication date: November 24, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Kwangduk Douglas Lee, Martin Jay Seamons, Sudha Rathi, Chiu Chan, Michael H. Lin
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Publication number: 20110281441Abstract: The present invention relates to a process for preparing an organic film on a selected zone at the surface of a photosensitive semiconductor substrate, characterized in that it comprises the following steps: (i) bringing a liquid solution comprising at least one organic adhesion primer into contact with at least said selected zone; (ii) polarization of the surface of said substrate to an electric potential more cathodic than the reduction potential of the adhesion primer used in step (i); and (iii) exposure of said selected zone to light radiation, the energy of which is at least equal to that of the band gap of said semiconductor.Type: ApplicationFiled: September 18, 2008Publication date: November 17, 2011Inventors: Julienne Charlier, Serge Palacin
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Patent number: 8030149Abstract: Embodiments relate to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. According to embodiments, a surface is subjected to a monochlorobenzene coating processing to cure the surface of the exposed photo resist so as not to react with developing solution and such a processed photo resist is developed to make the lower of the photo resist in the overhang structure so as to form an accurate pattern according to the clear removal of the oxide film, making it possible to simply manufacture the silicide and the non-silicide without performing an etching process by a subsequent cobalt deposition process.Type: GrantFiled: October 5, 2008Date of Patent: October 4, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: In-Cheol Baek
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Patent number: 8017465Abstract: A method for manufacturing an array substrate of liquid crystal display is performed with the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate; forming a photoresist layer on the source/drain metal layer through a triple-tone mask; performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist layer; performing a first ashing process on the photoresist layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process; performing a second ashing process on the photoresist layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and removing the remaining photoresist layer.Type: GrantFiled: September 24, 2009Date of Patent: September 13, 2011Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Seungjin Choi, Youngsuk Song, Seongyeol Yoo
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Patent number: 8017460Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.Type: GrantFiled: June 28, 2010Date of Patent: September 13, 2011Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Shu-Yu Chang, Wen-Hsiung Liu
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Publication number: 20110207331Abstract: There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.Type: ApplicationFiled: April 26, 2011Publication date: August 25, 2011Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Takahiro Sakaguchi, Tomoyuki Enomoto, Tetsuya Shinjo
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Publication number: 20110200790Abstract: The present invention concerns a method for localized grafting of an organic film in a selected area of an electrically conducting or semiconducting substrate, in the presence of a liquid solution containing at least one organic adhesion primer and at least one radically polymerizable monomer, different from the organic adhesion primer, by applying an electric potential to the substrate in the presence of a polarized microelectrode. The present invention also concerns an insulating organic film grafted on a conducting or semiconducting substrate, capable of being prepared using said method.Type: ApplicationFiled: March 26, 2009Publication date: August 18, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Julienne Charlier, Serge Palacin, Achraf Ghorbal, Federico Grisotto
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Patent number: 7989354Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.Type: GrantFiled: June 6, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Patent number: 7985667Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.Type: GrantFiled: June 26, 2009Date of Patent: July 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Sang-Hoon Cho
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Patent number: 7981812Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.Type: GrantFiled: July 3, 2008Date of Patent: July 19, 2011Assignee: Applied Materials, Inc.Inventors: Kang-Lie Chiang, Chia-Ling Kao
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Patent number: 7981706Abstract: A photoresist composition includes an alkali-soluble resin, a dissolution inhibitor including a quinone diazide compound, a first additive including a benzenol compound represented by the following Chemical Formula 1, a second additive including an acrylic copolymer represented by the following Chemical Formula 2 and an organic solvent. Accordingly, heat resistance of a photoresist pattern may be improved, and the photoresist pattern may be readily stripped. As a result, crack formation in the photoresist pattern may be reduced and/or prevented.Type: GrantFiled: September 28, 2010Date of Patent: July 19, 2011Assignees: Samsung Electronics Co., Ltd., Dongwoo Fine-ChemInventors: Jeong-Min Park, Jung-Soo Lee, Won-Young Chang, Eun-Sang Lee, In-Ho Yu, Seong-Hyeon Kim
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Patent number: 7981810Abstract: The present invention addresses this need by providing a method for forming transparent PECVD deposited ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers. Methods of the invention involve depositing the AHM using dilute hydrocarbon precursor gas flows and/or low process temperatures. The AHMs produced are transparent (having absorption coefficients of less than 0.1 in certain embodiments). The AHMs also have the property of high selectivity of the hard mask film to the underlying layers for successful integration of the film, and are suitable for use with 193 nm generation and below lithography schemes wherein high selectivity of the hard mask to the underlying layers is required. The lower temperature process also allows reduction of the overall thermal budget for a wafer.Type: GrantFiled: June 8, 2006Date of Patent: July 19, 2011Assignee: Novellus Systems, Inc.Inventors: Pramod Subramonium, Zhiyuan Fang, Jon Henri
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Patent number: 7972964Abstract: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines.Type: GrantFiled: June 7, 2006Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Chun-Gi You
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Publication number: 20110159701Abstract: The present disclosure provides a chemical liquid supply nozzle capable of suppressing the drying process of chemical liquid with a low cost. The chemical liquid supply nozzle is provided with a cutoff valve and a suction unit that sucks chemical liquid to a suction flow path at a nozzle main body connected to a front end of flow path member. Accordingly, the chemical liquid remaining at the downstream side of the cutoff valve after the chemical liquid is discharged, is sucked toward the upstream side of the cutoff valve and removed, to thereby suppress the drying and solidifying process of the chemical liquid at the chemical liquid flow path. Also, there is no need to block the chemical liquid flow path by sucking thinner at the downstream side of chemical liquid flow path, and the number of dummy dispense may be reduced, thereby reducing an overall operation cost of the process.Type: ApplicationFiled: December 20, 2010Publication date: June 30, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Tsunenaga NAKASHIMA, Shinichi HAYASHI, Akihiro FUJIMOTO, Takahiro OOKUBO
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Patent number: 7960288Abstract: A photoresist trimming gas compound is provided which will selectively remove a resist foot or scum from the lower portions of sidewalls of a photoresist. Additionally, the trimmer compound hardens or toughens an upper surface of the photoresist thereby strengthening the photoresist. The trimmer compound includes O2 and at least one other gaseous oxide and is typically utilized in a dry etching process after a trench has been formed in a photoresist. The other oxide gases, in addition to the O2 may include CO2, SO2 and NO2.Type: GrantFiled: October 9, 2007Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Shaun Crawford, Cuc K. Huynh, A. Gary Reid, Adam C. Smith, Thomas M. Wagner
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Patent number: 7956393Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: GrantFiled: September 21, 2009Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Sun-Young Hong, Young-Joo Choi, Byeong-Jin Lee, Nam-Seok Suh, Byung-Uk Kim, Suk-Il Yoon, Jong-Hyun Jeong, Sung-Gun Shin, Soon-Beom Huh, Se-Hwan Jung, Doo-Young Jang, Sun-Joo Park, Oh-Hwan Kweon
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Patent number: 7955988Abstract: A photoresist trimming gas compound is provided which will selectively remove a resist foot or scum from the lower portions of sidewalls of a photoresist. Additionally, the trimmer compound hardens or toughens an upper surface of the photoresist thereby strengthening the photoresist. The trimmer compound includes O2 and at least one other gaseous oxide and is typically utilized in a dry etching process after a trench has been formed in a photoresist. The other oxide gases, in addition to the O2 may include CO2, SO2 and NO2.Type: GrantFiled: September 27, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Shaun Crawford, Cuc K. Huynh, A. Gary Reid, Adam C. Smith, Thomas M. Wagner
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Patent number: 7939922Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.Type: GrantFiled: April 20, 2009Date of Patent: May 10, 2011Assignee: Intel CorporationInventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
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Publication number: 20110101507Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
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Publication number: 20110092078Abstract: A method of selectively attaching a capping agent to a Group IV semiconductor surface is disclosed. The method includes providing the Group IV semiconductor surface, the Group IV semiconductor surface including a set of covalently bonded Group IV semiconductor atoms and a set of surface boron atoms. The method also includes exposing the set of boron atoms to a set of capping agents, each capping agent of the set of capping agents having a central atom and a set of functional groups, wherein the central atom includes at least a lone pair of electrons; wherein a complex is formed between at least some surface boron atoms of the set of surface boron atoms and the central atom of at least some capping agents of the set of capping agents.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Inventors: Elena V. Rogojina, Maxim Kelman, Anthony Young Kim
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Publication number: 20110076797Abstract: A method for producing at least one pattern on a top surface of a support made from a material presenting a first thermal conductivity comprises a step of arranging of a mask made from a material presenting a second thermal conductivity and comprising at least one recess having a shape corresponding to that of the pattern, in contact with a bottom surface of the support, the ratio of the first conductivity over the second conductivity being greater than or equal to 2, or smaller than or equal to ½, throughout the duration of the method. The method further comprises a step of depositing on the top surface a solution comprising a material designed to form the pattern, and a step of evaporating the solution.Type: ApplicationFiled: September 10, 2010Publication date: March 31, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Mohamed BENWADIH
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Publication number: 20110076858Abstract: The invention provides methods for depositing a coating onto the entire backside of a semiconductor wafer. The methods of the invention address the deficiencies typically associated with deposition of coatings onto the backside of semiconductor wafers. Since the methods of the invention result in wafers wherein a coating has been dispensed all the way to the edge of the wafer, there is minimal chip flying during dicing, and minimal wafer breakage and chip breakage. In addition, the methods of the invention result in a marked decrease in waste when compared to traditional spin coating methods.Type: ApplicationFiled: December 9, 2010Publication date: March 31, 2011Inventor: Hoseung Yoo
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Patent number: 7910419Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.Type: GrantFiled: June 11, 2009Date of Patent: March 22, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Claire Fenouillet-Beranger, Philippe Coronel
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Publication number: 20110049731Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof.Type: ApplicationFiled: September 2, 2010Publication date: March 3, 2011Applicant: DESIGNER MOLECULES, INC.Inventors: Stephen M. Dershem, Farhad G. Mizori, James T. Huneke
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Patent number: 7898083Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 29, 2009Date of Patent: March 1, 2011Assignee: Texas Instruments IncorporatedInventor: Abram M Castro
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Patent number: 7892878Abstract: Provided are a method of manufacturing an organic light emitting device. The method includes forming an electron injection layer by vacuum co-depositing an organic semiconductor material having an electron mobility of about 1×10?6 cm2/V·s or more in an electric field of about 1×106 V/m and a metal azide.Type: GrantFiled: June 9, 2009Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-woo Lee, Tae-yong Noh, Haa-jin Yang, Byoung-ki Choi, Myeong-suk Kim, Dong-woo Shin
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Publication number: 20110034033Abstract: A method of manufacturing an electronic device, the method comprising: providing a substrate; forming a patterned layer of removable material on the substrate; depositing, using an indiscriminate deposition method, a layer of a surface energy modifying material over the substrate comprising the patterned layer of removable material; removing the removable material from the substrate thereby forming a patterned surface of the substrate with surface energy modifying material in those areas not previously covered by the removable material and no surface energy modifying material in those areas previously covered by the removable material; and depositing one or more active components from solution on the patterned surface of the substrate using an indiscriminate deposition technique whereby a patterned layer of the one or more active components is formed based on the pattern of surface energy modifying material on the substrate.Type: ApplicationFiled: December 17, 2008Publication date: February 10, 2011Inventors: Jonathan Halls, Gregory Whiting
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Patent number: 7879726Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.Type: GrantFiled: August 7, 2008Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Sik Park, Jun-Ho Yoon, Cheol-Kyu Lee, Joon-Soo Park
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Publication number: 20110021036Abstract: A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap.Type: ApplicationFiled: April 17, 2008Publication date: January 27, 2011Inventors: Greg Braecklmann, Marius Orlowski, Andreas Wild