Composed Of Alternated Layers Or Of Mixtures Of Nitrides And Oxides Or Of Oxynitrides, E.g., Formation Of Oxynitride By Oxidation Of Nitride Layer (epo) Patents (Class 257/E21.267)
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Publication number: 20120045905Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Inventors: Naonori AKAE, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
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Patent number: 8120124Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.Type: GrantFiled: February 28, 2007Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Er-Xuan Ping
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Patent number: 8110879Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.Type: GrantFiled: October 19, 2009Date of Patent: February 7, 2012Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.Inventors: Joaquin Torres, Laurent-Georges Gosset
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Patent number: 8110880Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.Type: GrantFiled: February 27, 2009Date of Patent: February 7, 2012Assignee: Northrop Grumman Systems CorporationInventor: John V. Veliadis
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Patent number: 8110490Abstract: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.Type: GrantFiled: August 15, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Da-Yuan Lee, Chi-Chun Chen, Hun-Jan Tao
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Patent number: 8105961Abstract: A method of creating a sensor that may include applying a first conductive material on a first portion of a substrate to form a reference electrode and depositing a first mask over the substrate, the first mask having an opening that exposes the reference electrode and a second portion of the substrate. The method may also include depositing a second conductive material into the opening in the first mask, the second conductive material being in direct contact with the reference electrode and depositing a second mask over the second conductive material, the second mask having an opening over the second portion of the substrate, the opening exposing a portion of the second conductive material which forms a working surface to receive a fluid of interest.Type: GrantFiled: August 6, 2009Date of Patent: January 31, 2012Assignee: Edwards Lifesciences CorporationInventor: Kenneth M. Curry
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Patent number: 8105936Abstract: Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.Type: GrantFiled: July 16, 2008Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Louis C. Hsu, Rajiv V. Joshi
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Patent number: 8101492Abstract: One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.Type: GrantFiled: September 23, 2009Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: John Power, Danny Pak-Chum Shum
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Patent number: 8101530Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.Type: GrantFiled: September 25, 2009Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Hsiung Huang, Chin-Hsiang Lin, Heng-Jen Lee, Heng-Hsin Liu
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Patent number: 8093640Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.Type: GrantFiled: July 13, 2009Date of Patent: January 10, 2012Assignee: Atmel CorporationInventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
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Patent number: 8093119Abstract: A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second side to form a cavity in corresponding to the diaphragm and a plurality of venting holes in the substrate. An isotropic etching process is performed from the first side and the second side of the substrate via vent holes to remove a dielectric portion of the structural dielectric layer for exposing a central portion of the diaphragm while an end portion is held by a residue portion of the structural dielectric layer.Type: GrantFiled: June 24, 2009Date of Patent: January 10, 2012Assignee: Solid State System Co., Ltd.Inventors: Tsung-Min Hsieh, Chien-Hsing Lee
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Patent number: 8093153Abstract: An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.Type: GrantFiled: December 18, 2009Date of Patent: January 10, 2012Assignee: United Microelectronics CorporationInventor: Ping-Chia Shih
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Patent number: 8084339Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.Type: GrantFiled: June 12, 2009Date of Patent: December 27, 2011Assignee: Novellus Systems, Inc.Inventors: George Andrew Antonelli, Jennifer O'Loughlin, Tony Xavier, Mandyam Sriram, Bart Van Schravendijk, Vishwanathan Rangarajan, Seshasayee Varadarajan, Bryan L. Buckalew
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Patent number: 8084832Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.Type: GrantFiled: September 15, 2009Date of Patent: December 27, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Young-Je Yun
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Patent number: 8084312Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.Type: GrantFiled: January 15, 2010Date of Patent: December 27, 2011Assignee: Texas Instruments IncorporatedInventors: Srinivasan Chakravarthi, P R Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider
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Patent number: 8076727Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.Type: GrantFiled: February 11, 2009Date of Patent: December 13, 2011Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 8067809Abstract: A semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by favorable nitrogen concentration profile of a gate insulating film, and a method for manufacturing the semiconductor device. The semiconductor device fabricating method operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, including introducing an oxynitriding species previously diluted by plasma excitation gas into a plasma processing apparatus, generating an oxynitriding species by a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.Type: GrantFiled: September 30, 2005Date of Patent: November 29, 2011Assignees: Tokyo Electron Limited, Tohoku UniversityInventors: Junichi Kitagawa, Shigenori Ozaki, Akinobu Teramoto, Tadahiro Ohmi
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Patent number: 8058095Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.Type: GrantFiled: June 23, 2009Date of Patent: November 15, 2011Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 8058151Abstract: A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.Type: GrantFiled: April 6, 2010Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Hao-Yi Tsai
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Patent number: 8048754Abstract: An object is to provide a single crystal semiconductor layer with extremely favorable characteristics without performing CMP treatment or heat treatment at high temperature. Further, an object is to provide a semiconductor substrate (or an SOI substrate) having the above single crystal semiconductor layer. A first single crystal semiconductor layer is formed by a vapor-phase epitaxial growth method on a surface of a second single crystal semiconductor layer over a substrate; the first single crystal semiconductor layer and a base substrate are bonded to each other with an insulating layer interposed therebetween; and the first single crystal semiconductor layer and the second single crystal semiconductor layer are separated from each other at an interface therebetween so as to provide the first single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. Thus, an SOI substrate can be manufactured.Type: GrantFiled: September 23, 2009Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Fumito Isaka, Sho Kato, Takashi Hirose
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Patent number: 8048735Abstract: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.Type: GrantFiled: June 15, 2007Date of Patent: November 1, 2011Assignee: Hitachi, Ltd.Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai
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Patent number: 8048787Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.Type: GrantFiled: September 14, 2009Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
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Patent number: 8030200Abstract: A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.Type: GrantFiled: September 23, 2009Date of Patent: October 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-Cheol Bae, Jong-Hyun Lee, Jong Tae Moon
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Patent number: 8021988Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.Type: GrantFiled: April 21, 2008Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kouichi Muraoka
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Patent number: 8017457Abstract: A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode.Type: GrantFiled: May 1, 2008Date of Patent: September 13, 2011Assignee: Elpida Memory, Inc.Inventor: Kazuhiko Kajigaya
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Patent number: 8017470Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.Type: GrantFiled: June 23, 2010Date of Patent: September 13, 2011Assignee: Round Rock Research, LLCInventors: Kevin L. Beaman, John T. Moore
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Patent number: 8008188Abstract: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.Type: GrantFiled: June 11, 2007Date of Patent: August 30, 2011Assignee: PPG Industries Ohio, Inc.Inventors: Kevin C. Olson, Alan E. Wang
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Patent number: 8008154Abstract: Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.Type: GrantFiled: August 8, 2008Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Jin Noh, Bon-Young Koo, Si-Young Choi, Ki-Hyun Hwang, Chul-Sung Kim, Sung-Kweon Baek, Jin-Hwa Heo
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Patent number: 8003531Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.Type: GrantFiled: September 29, 2009Date of Patent: August 23, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 7999295Abstract: A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.Type: GrantFiled: December 17, 2008Date of Patent: August 16, 2011Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hang-Ting Lue, Kuang-Yeu Hsieh
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Patent number: 7998876Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.Type: GrantFiled: March 11, 2010Date of Patent: August 16, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Toshiyuki Orita
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Publication number: 20110189862Abstract: Provided is a process of forming a silicon oxynitride film having concentration of hydrogen atoms below or equal to 9.9×1020 atoms/cm3 as measured by using secondary ion mass spectrometry (SIMS), using a plasma CVD device, which generates plasma by introducing microwaves into a process chamber by using a planar antenna having a plurality of apertures, by setting a pressure inside the process chamber within a range from 0.1 Pa to 6.7 Pa, and performing plasma CVD by using process gases including SiCl4 gas, nitrogen gas, and oxygen gas.Type: ApplicationFiled: September 29, 2009Publication date: August 4, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Tatsuo Nishita, Junya Miyahara, Masayuki Kohno
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Patent number: 7989354Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.Type: GrantFiled: June 6, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Patent number: 7985690Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: GrantFiled: June 4, 2009Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7981797Abstract: A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 25, 2008Date of Patent: July 19, 2011Assignee: Hynix Semiconductor Inc.Inventors: Cheol-Hwi Ryu, Hyung-Soon Park, Jong-Han Shin, Jum-Yong Park, Sung-Jun Kim
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Patent number: 7972941Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.Type: GrantFiled: July 1, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Hong, Gil-Heyun Choi, Jong-Myeong Lee, Geum-Jung Seong
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Patent number: 7972933Abstract: Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.Type: GrantFiled: March 29, 2010Date of Patent: July 5, 2011Assignee: Applied Materials, Inc.Inventors: Christopher S. Olsen, Johanes Swenberg, Udayan Ganguly, Theresa Kramer Guarini, Yonah Cho
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Publication number: 20110151672Abstract: An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventor: Ping-Chia SHIH
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Patent number: 7964513Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.Type: GrantFiled: August 24, 2009Date of Patent: June 21, 2011Assignee: ASM America, Inc.Inventors: Michael A. Todd, Keith D. Weeks, Christiaan J. Werkhoven, Christophe F. Pomarede
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Patent number: 7960286Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.Type: GrantFiled: June 17, 2009Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Han Liao, Tze-Liang Lee
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Patent number: 7951695Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.Type: GrantFiled: May 22, 2008Date of Patent: May 31, 2011Assignee: Freescale Semiconductor, Inc.Inventors: David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff, Ruiqi Tian
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Patent number: 7951685Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Sumitomo Chemical Company, LimitedInventors: Hiroyuki Sazawa, Naohiro Nishikawa, Masahiko Hata
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Patent number: 7947607Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.Type: GrantFiled: December 23, 2008Date of Patent: May 24, 2011Assignee: Macronix International Co., Ltd.Inventor: Chao-I Wu
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Patent number: 7943530Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.Type: GrantFiled: April 3, 2009Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Lidija Sekaric, Tymon Barwicz, Dureseti Chidambarrao
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Patent number: 7943495Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.Type: GrantFiled: June 4, 2009Date of Patent: May 17, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Hee-Don Jeong
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Patent number: 7943449Abstract: A method for producing a semiconductor structure and a semiconductor component are described.Type: GrantFiled: September 30, 2008Date of Patent: May 17, 2011Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Stefan Sedlmaier, Ralf Erichsen, Hans Weber, Oliver Haeberlen, Franz Hirler
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Patent number: 7939453Abstract: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics.Type: GrantFiled: February 26, 2009Date of Patent: May 10, 2011Assignees: Dai Nippon Printing Co., Ltd., RikenInventors: Masataka Kano, Kazuhito Tsukagoshi, Takeo Minari
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Patent number: 7939438Abstract: Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed.Type: GrantFiled: March 19, 2009Date of Patent: May 10, 2011Assignee: Rohm and Haas Electronic Materials LLCInventors: Gary Hamm, David L. Jacques, Carl J. Colangelo
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Patent number: 7939915Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.Type: GrantFiled: October 13, 2009Date of Patent: May 10, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Hok Min Ho, Ching Tien Ma, Woei Ji Song
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Patent number: 7935638Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.Type: GrantFiled: September 24, 2009Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin