Deposition Of Layer Comprising Metal, E.g., Metal, Alloys, Metal Compounds (epo) Patents (Class 257/E21.295)
-
Publication number: 20130095649Abstract: Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath.Type: ApplicationFiled: October 17, 2011Publication date: April 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, John Anthony Fitzsimmons, David E. Speed, Keith Kwong Hon Wong
-
Publication number: 20130084701Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide(CuO) to copper(Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.Type: ApplicationFiled: December 29, 2011Publication date: April 4, 2013Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Meimei GU, Duoyuan HOU, Jun XU, Ke WANG
-
Patent number: 8399313Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.Type: GrantFiled: July 19, 2011Date of Patent: March 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kengo Akimoto, Hotaka Maruyama
-
Patent number: 8389393Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.Type: GrantFiled: July 29, 2009Date of Patent: March 5, 2013Assignee: Massachusetts Institute of TechnologyInventors: Silvija Grade{hacek over (c)}ak, Chun-Hao Tseng, Sung Keun Lim
-
Publication number: 20130052823Abstract: A system is provided that includes a power supply connectable to a semiconductor wafer including opposing, major front and back surfaces joined by a circumferential side, with the wafer undergoing processing including electroplating a damascene layer on the wafer. The system also includes an arrangement configured to apply a polymer coating to the side of the wafer before electroplating the damascene layer, with the system being configured to apply the polymer coating in accordance with an electrophoresis technique driven by the power supply. In this regard, the polymer coating is applied to the side but not at least a portion of the front and back surfaces of the wafer, and the polymer coating provides a barrier to formation of the damascene layer on the side of the wafer.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Meng Tsung Ko, Yung Tai Hung, Chin Ta Su
-
Publication number: 20130040449Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.Type: ApplicationFiled: October 16, 2012Publication date: February 14, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
-
Publication number: 20130034959Abstract: An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Inventors: Jason CHEN, Nakano Liu, Winson Shao, Wen Chu, Chang-Hwang Hua
-
Publication number: 20130029488Abstract: Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ming Cai, Dechao Guo, Chun-chen Yeh
-
Patent number: 8354337Abstract: [Problems]There is provided a metal oxide film forming method capable of controlling a film thickness of a metal oxide even if the metal oxide is subject to a self-limited thickness. [Means for Solving the Problems] A metal oxide film forming method includes a process (1) of supplying a metal source gas to a surface of a base before a temperature of the base reaches a film formation temperature of a metal oxide film; and a process (2) of setting the temperature of the base to be equal to or higher than the film formation temperature and forming the metal oxide film on the base by making a reaction between the metal source gas supplied to the surface of the base and residual moisture on the surface of the base.Type: GrantFiled: May 18, 2010Date of Patent: January 15, 2013Assignee: Tokyo Electron LimitedInventors: Kenji Matsumoto, Hidenori Miyoshi, Hitoshi Itoh, Hiroshi Sato
-
Publication number: 20130009328Abstract: An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the alignment mark, by which the color of the background of the alignment mark is stable and reliable. By such arrangement, the contrast between colors of a main pattern and the background of the alignment mark can be significantly improved, without considering a problem the homogeneity of manufacturing process. If the alignment mark is applied for manufacturing of a display, a recognition successful rate of alignment to attach an integrated circuit (IC) to a panel of the display is increased.Type: ApplicationFiled: July 3, 2012Publication date: January 10, 2013Applicant: ORISE TECHNOLOGY CO., LTD.Inventors: Tai-Ho Wang, Jia-Luen Peng, Hung-Sheng Yu
-
Patent number: 8349738Abstract: Compositions and methods for forming a metal-containing thin film on a substrate. A reactor and at least one substrate in the reactor are provided. A metal-containing bis-?-diketiminate precursor is introduced into the reactor. The reactor is maintained at a set temperature and pressure, and the precursor is contacted with the substrate to form a metal-containing film on the substrate.Type: GrantFiled: November 10, 2011Date of Patent: January 8, 2013Assignees: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude, American Air Liquide, Inc.Inventors: Clement Lansalot-Matras, Christian Dussarrat, Vincent M. Omarjee, Cheng-Fang Hsiao
-
Publication number: 20120323008Abstract: The present application provides precursor compounds useful for deposition of a group 11 metal on a substrate, for example, a microelectronic device substrate, as well as methods of synthesizing such precursor compounds. The precursor compounds provided are mono-metallic compounds comprising a diaminocarbene (DAC) having the general formula: “DAC-M-X”, where the diaminocarbene is an optionally substituted, saturated N-heterocyclic diaminocarbene (sNHC) or an optionally substituted acyclic diaminocarbene, M is a group 11 metal, such as copper, silver or gold; and X is an anionic ligand. Also provided are methods of synthesizing the precursor compounds, metal deposition methods utilizing such precursor compounds, and to composite materials, such as, e.g., microelectronic device structures, and products formed by use of such precursors and deposition methods.Type: ApplicationFiled: May 10, 2012Publication date: December 20, 2012Inventors: Sean BARRY, Jason Coyle, Timothy James Clark, Jeffrey J.M. Hastie
-
Patent number: 8334208Abstract: A film forming method includes arranging a target substrate to be processed in a chamber; supplying a processing gas including a chlorine containing gas through a supply path to the chamber in which the target substrate is arranged; and arranging a Ti containing unit in the supply path of the processing gas and making a reaction between the chlorine containing gas of the processing gas and Ti of the Ti containing unit by bringing the chlorine containing gas into contact with the Ti containing unit, when the processing gas is supplied to the chamber. The method further includes depositing Ti on a surface of the target substrate by a thermal reaction by supplying to the target substrate a Ti precursor gas produced by the reaction between the chlorine containing gas and Ti of the Ti containing unit while heating the target substrate provided in the chamber.Type: GrantFiled: June 10, 2011Date of Patent: December 18, 2012Assignee: Tokyo Electron LimitedInventor: Kensaku Narushima
-
Patent number: 8329569Abstract: Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO4) as a ruthenium precursor. In some embodiments for forming ruthenium, methods include forming a seed layer, and forming a ruthenium layer on the seed layer, using RuO4. In other embodiments, methods include performing atomic layer deposition cycles, which include using RuO4 and another ruthenium-containing co-precursor. In yet other embodiments, methods include adsorbing a reducing agent over a substrate, and supplying RuO4 to be reduced to ruthenium by the adsorbed reducing agent. In other embodiments for forming ruthenium dioxide, methods may include providing an initial seed layer formed of, for example, an organic compound, and supplying RuO4 over the seed layer.Type: GrantFiled: July 2, 2010Date of Patent: December 11, 2012Assignee: ASM America, Inc.Inventor: Dong Li
-
Patent number: 8328585Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.Type: GrantFiled: August 7, 2009Date of Patent: December 11, 2012Assignee: Texas Instruments IncorporatedInventors: Gregory Charles Herdt, Joseph W. Buckfeller
-
Publication number: 20120309193Abstract: A non-catalytic palladium precursor composition is disclosed, including a palladium salt and an organoamine, wherein the composition is substantially free of water. The composition permits the use of solution processing methods to form a palladium layer on a wide variety of substrates, including in a pattern to form circuitry or pathways for electronic devices.Type: ApplicationFiled: November 7, 2011Publication date: December 6, 2012Applicant: Xerox CorporationInventors: Yiliang Wu, Ping Liu
-
Patent number: 8318581Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.Type: GrantFiled: November 18, 2011Date of Patent: November 27, 2012Assignee: Infineon Technologies AGInventors: Karl-Heinz Mueller, Bernhard Winkler, Robert Gruenberger
-
Patent number: 8318596Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.Type: GrantFiled: February 11, 2010Date of Patent: November 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tin-Hao Kuo, Chen-Shien Chen, Ching-Wen Hsiao
-
Publication number: 20120295439Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.Type: ApplicationFiled: August 1, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Christian Lavoie, Tak H. Ning, Ahmet S. Ozcan, Bin Yang, Zhen Zhang
-
Publication number: 20120256276Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
-
Publication number: 20120241946Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.Type: ApplicationFiled: December 6, 2010Publication date: September 27, 2012Applicant: STATS CHIPPAC, LTD.Inventor: Rajendra D. Pendse
-
Patent number: 8274151Abstract: An object including at least one graphic element, including at least one layer including at least one metal and etched according to a pattern of the graphic element, a first face of the layer being positioned opposite a face of at least one at least partly transparent substrate, a second face, opposite to the first face, of the layer being covered with at least one passivation layer fixed to at least one face of at least one support by wafer bonding and forming with the support a monolithic structure, and the layer including at least at the second face, at least one area including the metal and at least one semiconductor.Type: GrantFiled: January 23, 2009Date of Patent: September 25, 2012Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Alain Rey, Chrystel Deguet, Laurent Vandroux
-
Publication number: 20120220127Abstract: A manufacturing method of a semiconductor device includes: forming a metal layer having a surface containing gold; growing a first silicon nitride layer in contact with the metal layer by a plasma-enhanced vapor deposition method; growing a second silicon nitride layer in contact with the first silicon nitride layer by a plasma-enhanced vapor deposition method at a layer-forming rate higher than that of the first silicon nitride layer, the second silicon nitride layer having a silicon composition ratio smaller than that of the first silicon nitride layer.Type: ApplicationFiled: February 28, 2012Publication date: August 30, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Tsutomu Komatani
-
Patent number: 8242017Abstract: A method for forming an integrated circuit device including an interconnect structure, e.g., copper dual damascene. The method includes providing a substrate and forming an interlayer dielectric layer overlying the substrate. The method also includes patterning the interlayer dielectric layer to form a contact structure and forming a barrier metal layer overlying the contact structure. The method includes forming a seed layer comprising copper bearing species overlying the barrier metal layer and applying an oxygen bearing species to treat the seed layer to cause an oxide layer of predetermined thickness to form on the seed layer. The method protects the seed layer from contamination using the oxide layer while the substrate is transferred from the step of applying the seed layer and contacts a copper bearing material in liquid form overlying the oxide layer to dissolve the oxide layer while forming a thickness of copper bearing material using a plating process to begin filling the contact structure.Type: GrantFiled: March 7, 2008Date of Patent: August 14, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Yang Hui Xiang, Qing Tang Jiang
-
Publication number: 20120196441Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.Type: ApplicationFiled: September 30, 2010Publication date: August 2, 2012Applicant: ALCHIMERInventors: Vincent Mevellec, Dominique Suhr
-
Patent number: 8232154Abstract: A method for fabricating a semiconductor device is provided. A high dielectric constant (high-k) layer and a work function metal layer are formed in sequence on a substrate. A hard mask layer is formed on the work function metal layer, where the material of the hard mask layer is lanthanum oxide. The work function metal layer is patterned by using the hard mask layer as a mask. The hard mask layer is then removed. Afterwards, a gate structure is formed on the substrate.Type: GrantFiled: September 21, 2009Date of Patent: July 31, 2012Assignee: United Microelectronics Corp.Inventors: Chin-Cheng Chien, Chun-Hsien Lin, Chiu-Hsien Yeh
-
Publication number: 20120190194Abstract: Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth site to a polymer source and growing a polymer tube at a rate of at least 80 micrometer per hour at the growth site. The method or system can provide selectivity by providing a growth site on a substrate by patterning a metal, such as copper, that provides a seed site for the polymer. Non-selected sites can be coated with a polymer growth inhibitor, such as polyimide or silicon nitride.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Inventors: Eyal Bar-sadeh, Nuriel Amir, Alexander Ripp, Yakov Shor, Dror Horvitz
-
Publication number: 20120184100Abstract: A chemically amplified positive resist composition comprising (A) a substantially alkali insoluble polymer having an acidic functional group protected with an acid labile group, (B) an acid generator, and (C) a perfluoroalkyl ethylene oxide adduct or a nonionic fluorinated organosiloxane compound is coated, exposed to UV radiation having a wavelength of at least 150 nm, and developed. The composition has advantages of uniformity and minimized edge crown upon coating, and no scum formation after development.Type: ApplicationFiled: January 19, 2012Publication date: July 19, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hiroyuki Yasuda, Katsuya Takemura, Noriyuki Koike
-
Publication number: 20120184101Abstract: In a chemically amplified positive resist composition comprising a base resin and an acid generator in a solvent, the base resin contains both an alkali-insoluble or substantially alkali-insoluble polymer having an acid labile group-protected acidic functional group having a Mw of 1,000-500,000 and an alkyl vinyl ether polymer having a Mw of 10,000-500,000. The composition forms on a substrate a resist film of 5-100 ?m thick which can be briefly developed to form a pattern at a high sensitivity and a high degree of removal or dissolution to bottom.Type: ApplicationFiled: January 19, 2012Publication date: July 19, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hiroyuki Yasuda, Katsuya Takemura
-
Publication number: 20120178254Abstract: A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.Type: ApplicationFiled: March 20, 2012Publication date: July 12, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Youn-soo KIM, Jae-hyoung Choi, Kyu-ho Cho, Wan-don Kim, Jae-soon Lim, Sang-yeol Kang
-
Publication number: 20120168955Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.Type: ApplicationFiled: January 3, 2011Publication date: July 5, 2012Applicant: Macronix International Co., Ltd.Inventors: Shih-Hung Chen, Hang-Ting Lue
-
Publication number: 20120161321Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani, Seongjun Park
-
Publication number: 20120139113Abstract: A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
-
Patent number: 8193083Abstract: A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.Type: GrantFiled: September 4, 2008Date of Patent: June 5, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Sadayoshi Horii, Yoshinori Imai, Mika Karasawa
-
Publication number: 20120126415Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.Type: ApplicationFiled: November 18, 2010Publication date: May 24, 2012Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
-
Publication number: 20120122313Abstract: Compositions and methods for forming a metal-containing thin film on a substrate. A reactor and at least one substrate in the reactor are provided. A metal-containing bis-?-diketiminate precursor is introduced into the reactor. The reactor is maintained at a set temperature and pressure, and the precursor is contacted with the substrate to form a metal-containing film on the substrate.Type: ApplicationFiled: November 10, 2011Publication date: May 17, 2012Applicants: American Air Liquide, Inc., L'Air Liquide Societe Anonyme pour I'Etude et I'Exploitation des Procedes Georges ClaudeInventors: Christian Dussarrat, Clement Lansalot-Matras, Vincent M. Omarjee, Cheng-Fang Hsiao
-
Publication number: 20120094412Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.Type: ApplicationFiled: December 22, 2011Publication date: April 19, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Osamu NAKAMURA, Klyofumi Ogino
-
Publication number: 20120070981Abstract: The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Inventors: Scott B. Clendenning, James M. Blackwell, Patricio Romero, John Plombon
-
Publication number: 20120064716Abstract: A film forming apparatus is used in a semiconductor manufacturing process and a method for producing a barrier film is used for a semiconductor. When a metallic gas and a reactive gas are alternatively flown, a back-flow preventing gas and an auxiliary gas are flown, the reactive gas and the auxiliary gas are moved with the flow of the back-flow preventing gas, and radicals are produced by being in contact with them to a catalytic material. Since the metallic material gas is not in contact with the catalytic material, the catalytic material is not degraded. A shower plate may be disposed between a radical producing chamber and a reaction chamber, so that the radicals are fed into the reaction chamber through holes. Thus, a barrier film having low resistance and excellent coverage is formed.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Applicant: ULVAC, Inc.Inventor: Masamichi Harada
-
Publication number: 20120052650Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: ApplicationFiled: November 3, 2011Publication date: March 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin R. Shea, Thomas M. Graettinger
-
Patent number: 8125085Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.Type: GrantFiled: June 9, 2009Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Kazuyoshi Maekawa, Kenichi Mori, Kazuyuki Omori, Yuki Koyama
-
Patent number: 8114741Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.Type: GrantFiled: May 13, 2010Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Shiu-Ko JangJian, Wan-Ting Huang, Yu-Jen Chien, Phil Sun
-
Publication number: 20120035351Abstract: Sterically hindered imidazole ligands are described, along with their synthesis, which are capable of coordinating to Group 2 metals, such as: calcium, magnesium, strontium, in an eta-5 coordination mode which permits the formation of monomeric or dimeric volatile complexes. A compound comprising one or more polysubstituted imidazolate anions coordinated to a metal selected from the group consisting of barium, strontium, magnesium, radium or calcium or mixtures thereof. Alternatively, one anion can be substituted with and a second non-imidazolate anion.Type: ApplicationFiled: January 28, 2011Publication date: February 9, 2012Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: John Anthony Thomas Norman, Melanie K. Perez, Moo-Sung Kim
-
Patent number: 8105867Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.Type: GrantFiled: May 19, 2009Date of Patent: January 31, 2012Assignee: SanDisk 3D LLCInventors: George Matamis, Henry Chien, James K Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E Scheuerlein
-
Patent number: 8105945Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.Type: GrantFiled: February 25, 2011Date of Patent: January 31, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Osamu Nakamura, Kiyofumi Ogino
-
Patent number: 8101507Abstract: There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing method includes: an etching process for etching a low dielectric insulating film formed on a substrate; a CO2 plasma process for exposing the substrate to CO2 plasma after the etching process; and a UV process for irradiating UV to the low dielectric insulating film after the CO2 plasma process.Type: GrantFiled: October 16, 2009Date of Patent: January 24, 2012Assignee: Tokyo Electron LimitedInventors: Ryuichi Asako, Gousuke Shiraishi, Shigeru Tahara
-
Publication number: 20120012922Abstract: A semiconductor device and a method of manufacturing the same are provided. Upon forming source or drain at a lower part of the pillar pattern, a silicon oxide layer (barrier layer) is formed inside the pillar pattern to prevent the pillar pattern from being electrically floated. Furthermore, impurities are diffused to a vertical direction (longitudinal direction) of the pillar pattern to overlay junction between the semiconductor substrate and source or drain formed at a lower part of the pillar pattern that leads to improvement of a current characteristic.Type: ApplicationFiled: November 12, 2010Publication date: January 19, 2012Applicant: Hynix Semiconductor Inc.Inventor: Tae Su JANG
-
Publication number: 20120007231Abstract: A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Wei Sen CHANG
-
Publication number: 20120007230Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu
-
Publication number: 20110318924Abstract: The invention relates to a method for deposition of at least one electrically conducting film (20) on a substrate (30), comprising the steps: selecting a layer (10) of a film material, wherein the layer (10) comprises a mask (40) on a front side (11) and wherein the layer (10) and the mask (40) are one piece, positioning the front side (11) of the layer (10) upon the substrate (30), applying at least one laser pulse (120) onto a back side (12) of the layer (10), so as to melt and to vaporize at least parts of the layer (10) such that melt droplets (110) are propelled toward and deposited upon said substrate (30), forming the film (20), wherein at least one slot (45) of the mask (40) limits the distribution of said melt droplets (110).Type: ApplicationFiled: January 11, 2010Publication date: December 29, 2011Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Dietrich Bertram, Jochen Stollenwerk, Johannes Krijne, Holger Schwab, Edward W. A. Young, Jeroen H. A. M. Van Buul, Andres Gasser, Konrad Wissenbach, Christian Vedder, Norbert Pirch