Diode (epo) Patents (Class 257/E21.352)
  • Patent number: 10676642
    Abstract: Provided are: a crosslinked organopolysiloxane which has properties intermediate between a dimethylpolysiloxane oil and a gel-like crosslinked siloxane; and a method for producing the crosslinked organopolysiloxane. An oil-like organopolysiloxane which is produced by: adding a compound having a siloxane unit represented by formula (3) to a gel-like silicone, wherein the gel-like silicone is produced by a hydrosilylation reaction of an organopolysiloxane having an alkenyl group with an organohydrogenpolysiloxane having a hydrogen atom bonded to a silicon atom in the presence of a platinum-group metal catalyst; and then equilibrating the resultant product with an acid or alkali catalyst. R12SiO2/2??(3) (R1 represents a group selected from a monovalent hydrocarbon group having no aliphatic unsaturated bond and an alkenyl group represented by the formula: —(CH2)a—CH?CH2 (wherein a represents a numerical value of 0 to 6), and the average polymerization degree of formula (3) is 3 to 2,000).
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 9, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Toshiaki Ihara
  • Patent number: 9660154
    Abstract: Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 23, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Salman Akram, Jyoti Kiron Bhardwaj
  • Patent number: 9029921
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8999770
    Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 7, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Patent number: 8993368
    Abstract: Method for manufacturing a microelectronic device from a first substrate (10), including the production of at least one electronic component in the semi-conductor substrate after transferring the first substrate (10) onto a second substrate (20), characterized in that it comprises: a first phase carried out prior to the transfer, and including forming at least one pattern made of a sacrificial material in a layer of the first substrate (10), a second phase carried out after the transfer and including the substitution of the electronic component for the pattern.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: March 31, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Umberto Rossini
  • Patent number: 8993447
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 31, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
  • Patent number: 8987753
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8969143
    Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
  • Patent number: 8963167
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 24, 2015
    Assignee: Neokismet, LLC
    Inventors: Jawahar M. Gidwani, Anthony C. Zuppero
  • Patent number: 8963197
    Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Myung Soo Han, Seung Ho Jang, Won Seok Choi
  • Patent number: 8952512
    Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 10, 2015
    Assignee: China Wafer Level CSP Ltd.
    Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
  • Patent number: 8946728
    Abstract: A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles, and having a void therein. A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles or quantum dots, and having a void therein.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu Sang Kim
  • Patent number: 8946784
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Patent number: 8945979
    Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yun-Ho Chang
  • Patent number: 8928052
    Abstract: An optoelectronic semiconductor chip has a semiconductor layer sequence having an active layer that generates radiation between a layer of a first conductivity type and a layer of a second conductivity type. The layer of the first conductivity type is adjacent to a front side of the semiconductor layer sequence. The semiconductor layer sequence contains at least one cutout extending from a rear side, lying opposite the front side, of the semiconductor layer sequence through the active layer to the layer of the first conductivity type. The layer of the first conductivity type is electrically connected through the cutout by means of a first electrical connection layer which covers the rear side of the semiconductor layer sequence at least in places.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 6, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Lutz Hoeppel, Patrick Rode, Matthias Sabathil
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8916872
    Abstract: A method of forming a stacked low temperature diode and related devices. At least some of the illustrative embodiments are methods comprising forming a metal interconnect disposed within an inter-layer dielectric. The metal interconnect is electrically coupled to at least one underlying integrated circuit device. A barrier layer is deposited on the metal interconnect and the inter-layer dielectric. A semiconductor layer is deposited on the barrier layer. A metal layer is deposited on the semiconductor layer. The barrier layer, the semiconductor layer, and the metal layer are patterned. A low-temperature anneal is performed to induce a reaction between the patterned metal layer and the patterned semiconductor layer. The reaction forms a silicided layer within the patterned semiconductor layer. Moreover, the reaction forms a P-N junction diode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 23, 2014
    Assignee: Inoso, LLC
    Inventors: Ziep Tran, Kiyoshi Mori, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 8906752
    Abstract: Ink compositions comprising polythiophenes and methicone that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 9, 2014
    Assignee: Kateeva, Inc.
    Inventors: Inna Tregub, Rajsapan Jain, Michelle Chan
  • Patent number: 8900912
    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: December 2, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 8896037
    Abstract: A solid-state imaging device including: a semiconductor layer; a charge accumulation region configured to be formed inside the semiconductor layer and serve as part of a photodiode; and a reflective surface configured to be disposed inside or under the charge accumulation region and be so formed as to reflect light that has passed through the charge accumulation region and direct the light toward a center part of the charge accumulation region.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Harumi Ikeda, Masashi Nakazawa
  • Patent number: 8884336
    Abstract: A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: November 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8872180
    Abstract: A production method for a liquid crystal display device having a plurality of thin film transistors (TFTs) including reflection sections disposed to correspond to a plurality of pixels includes: a step of forming on a substrate a metal layer having apertures; a step of forming a semiconductor layer on the metal layer; a step of forming a protection layer on the semiconductor layer; a step of forming a resist layer on the protection layer; a photolithography step of irradiating the resist layer with light through the metal layer to pattern the protection layer by photolithography technique; and a step of stacking a reflective layer on the patterned protection layer. A plurality of bumps are formed from the protection layer in the photolithography step, and a plurality of bumps corresponding to the plurality of bumps of the protection layer are formed on the reflective layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 28, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 8871574
    Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8872194
    Abstract: An illumination device is disclosed. The illumination device includes a light source a pre-dip material that at least partially encapsulates the light source. The pre-dip material may include one or both of thermally-conductive particles and a cyclo-aliphatic composition. The pre-dip material may further include a resin and a hardener for the resin. Methods of manufacturing an illumination device are also disclosed.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kum Soon Wong, Yean Chon Yaw, Kit Lai Wong
  • Patent number: 8847367
    Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 30, 2014
    Assignee: Nippon Steel & Sumikin Chemical Co., Ltd.
    Inventors: Takayuki Fukumatsu, Ikumi Ichihashi, Hiroshi Miyazaki, Atsushi Oda
  • Patent number: 8847059
    Abstract: Electrical energy is generated in a device that includes an integrated circuit which produces thermal flux when operated. A substrate supports the integrated circuit. A structure is formed in the substrate, that structure having a semiconductor p-n junction thermally coupled to the integrated circuit. Responsive to the thermal flux produced by the integrated circuit, the structure generates electrical energy. The generated electrical energy may be stored for use by the integrated circuit.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Thomas Skotnicki, Stephane Monfray
  • Patent number: 8828766
    Abstract: A light-emitting device and a method of fabricating the same, in which the light emission characteristics of the light-emitting device in the UV range are maximized such that a high-efficiency light-emitting device can be produced at low cost. For this, the method includes the step of forming a zinc oxide light-emitting layer on a base substrate, the zinc oxide light-emitting layer including zinc oxide doped with a dopant; and activating the dopant by rapidly heat-treating the zinc oxide light-emitting layer, so that light emission in an ultraviolet range is increased.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 9, 2014
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: YoungZo Yoo, SeoHyun Kim, JeongWoo Park, Taejung Park, Gun Sang Yoon
  • Patent number: 8816404
    Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 26, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YoungJoon Kim, SangMi Park, YongHyuk Jeong
  • Patent number: 8809981
    Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Ando, Toru Gotoda, Toru Kita
  • Patent number: 8803276
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
  • Patent number: 8785326
    Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
  • Patent number: 8772826
    Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: July 8, 2014
    Assignee: KYOCERA Corporation
    Inventors: Hideaki Asao, Rui Kamada, Shuichi Kasai, Seiji Oguri, Isamu Tanaka, Nobuyuki Horiuchi, Kazumasa Umesato
  • Patent number: 8759935
    Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8753947
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8753946
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United States
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8748938
    Abstract: There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N+ region and a P region are formed from the bottom. On an upper side surface of this P region, an N region and a P+ region are formed from an inner side of the island-shaped semiconductor. Above the P region, a P+ region is formed. By setting the P+ region and the P+ region to have a low-level voltage and setting the signal line N+ region to have a high-level voltage that is higher than the low-level voltage, signal charges accumulated in the N region are discharged to the signal line N+ region via the P region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: June 10, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 8741702
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8735985
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 27, 2014
    Assignee: The Invention Science Fund I, LLC
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20140110814
    Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8698227
    Abstract: A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 15, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Samuel Menard
  • Patent number: 8686515
    Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Samuel Menard
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8664691
    Abstract: A silicon photomultiplier maintains the photon detection efficiency high while increasing a dynamic range, by reducing the degradation of an effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 4, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Joon Sung Lee
  • Patent number: 8659162
    Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 25, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
  • Publication number: 20140043096
    Abstract: Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Inventor: Adrian FINNEY
  • Patent number: 8648360
    Abstract: A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 11, 2014
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Kuan-Yu Chen
  • Publication number: 20140027773
    Abstract: A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Andreas Meiser
  • Patent number: 8637339
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Neokismet L.L.C.
    Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
  • Patent number: 8633521
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 21, 2014
    Assignee: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov