Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.

Abstract: A method is provided for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. An N+ region is implanted in a P-type substrate and a P-type well separates the N+ region from the shallow trench isolation (STI) structure. At least a P+ region is formed over the N+ region and overlapping at least part of the P-type well and a substrate portion between the N+ region and P-type well. The space between the N+ region and a damaged region adjacent the STI is greater than the expansion distance of the depletion region between the N+ region and the P-type well. The junctions of the various features are optimized to maximize a photosensitive response for the wavelength of the absorbed light as well as for reducing or eliminating electrical leakage.

Abstract: A method of trimming the critical dimension of an isolated line to a greater extent than a dense line is provided. A mask is formed of an organic material over the etch layer wherein the mask has at least a first region with a first pattern density and a second region with a second pattern density. A surface area of the organic material in the first region is measured. A surface area of the organic material in the second region is measured. A reverse bias trim of the mask is provided, wherein a ratio of a trim rate of the organic material in the first region to a trim rate of the organic material in the second region is related to a ratio of the measured surface area of the organic material in the first region to the measured surface area of the organic material in the second region.

Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active region, and a second semiconductor layer of a second conductivity type. First and second contacts are connected to the first and second semiconductor layers. In some embodiments at least one of the first and second contacts has a thickness greater than 3.5 microns. In some embodiments, a first heat extraction layer is connected to one of the first and second contacts. In some embodiments, one of the first and second contacts is connected to a submount by a solder interconnect having a length greater than a width. In some embodiments, an underfill is disposed between a submount and one of the first and second interconnects.

Abstract: A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent pixels and their associated photodiodes is provided. The shared active area region isolates the two adjacent photodiodes and provides good substrate to surface pinned layer contact without the presence of n? type dopant ions and due to the presence of p-type dopant ions. As a result, the size of the imager can be reduced and the photodiodes of the two adjacent pixels have increased capacitance.