Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.

Abstract: A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer containing silicon nitride on a semiconductor layer. The method includes forming a side wall film on a side wall of the mask layer. The method includes etching the semiconductor layer using the mask layer and the side wall film to form a gate trench. The method includes forming a gate electrode in the gate trench. The method includes removing the side wall film and forming a base region and a source region in the semiconductor layer using the mask layer. The method includes forming an interlayer film covering the semiconductor layer, the gate electrode and the mask layer, and containing silicon oxide. The method includes forming a contact trench, by using the interlayer film as a mask, in a portion of the semiconductor layer under a portion where the mask layer is removed.

Abstract: Disclosed is a method of manufacturing a semiconductor device comprising: forming a first layer on a sidewall of a trench formed on a main surface of a semiconductor substrate, filling up the trench with a protective film, etching back the protective film by a dry etching method so that a height of a surface of the protective film is lower than an opening of the trench and removing the first layer exposed by the etching-back.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.

Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

Abstract: A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.

Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.

Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

Abstract: A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.

Abstract: Disclosed is a power semiconductor device, in particular, a trench type power semiconductor device for use in power electronic devices. A method of manufacturing the same is provided. The method of manufacturing the power semiconductor device adopts a trench MOSFET to decrease the size of the device, in place of a vertical type DMOSFET, under a situation in which the cost must be lowered owing to excessive cost competition. As the manufacturing process is simplified and the characteristics are improved, the cost is reduced, resulting in mass production and the creation of profit.

Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Abstract: Semiconductor switching devices include a first wide band-gap semiconductor layer having a first conductivity type. First and second wide band-gap well regions that have a second conductivity type that is opposite the first conductivity type are provided on the first wide band-gap semiconductor layer. A non-wide band-gap semiconductor layer having the second conductivity type is provided on the first wide band-gap semiconductor layer. First and second wide band-gap source/drain regions that have the first conductivity type are provided on the first wide band-gap well region. A gate insulation layer is provided on the non-wide band-gap semiconductor layer, and a gate electrode is provided on the gate insulation layer.

Abstract: A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.

Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Abstract: This invention has a purpose to provide an insulated gate-type semiconductor device and its manufacturing method in which a decrease in gate insulation dielectric strength voltage and a reduction in manufacturing costs are both achieved. First, (a) a CZ bulk substrate is prepared. Next, (b) P? diffused layer and N+ diffused layer 31 are formed by executing processes such as ion implantation and thermal diffusion treatment. Further (c) a gate trench is formed by reactive ion etching. Next, (d) a gate insulation film containing carbon of 1.0×1018 atoms/cm3 is formed on the wall face of a gate trench according to a CVD method and, annealing is subsequently performed. As a consequence, a low defect area is formed in the vicinity of an interface between the CZ bulk substrate and the gate insulation film.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

Abstract: An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween.

Abstract: A method for manufacturing a semiconductor device having a buried gate is provided. A gate conductive layer is first formed in the peri region before a bit line contact is formed in the cell region, so that a fabrication process is simplified and the problem caused by a step height between the cell region and the core/peri region is not encountered.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region.

Abstract: A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a gate insulating film; and a diffusion layer formed close to the trench; on a semiconductor substrate, and also includes an opening portion positioned on one surface of the semiconductor substrate; a pair of first inner walls positioned in a side of the device isolation insulating film and connected with the opening portion; a pair of second inner walls positioned in a side of the active region and connected with the opening portion; and a bottom portion positioned opposite to the opening portion and connected with the first inner walls and the second inner walls, wherein a cross sectional outline of the second inner wall is substantially linear, and a burr generated inside the trench is removed or redu

Abstract: A manufacturing method is provided for a power semiconductor device that enables reducing its on-state voltage and power loss. The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n? layer 1, to reach into a location of the n? layer 1. At the lower ends of each of the trench gates 3, bottom portions 3d are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n? layer 1. In addition, the extending end of one of the bottom portions 3d opposes that of the other bottom portion, on the extending side of the bottom portions 3d, and the interspace between each pair of adjacent bottom portions 3d is set narrower than any other interspace between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n? layer 1.

Abstract: A method of manufacturing a semiconductor device includes: a first step of forming an STI region and an active region surrounded by the STI region on a semiconductor substrate; a second step of forming a protection film protecting a shoulder part of the STI region in a boundary between the active region and the STI region; a third step of forming a gate trench in the active region so as to leave a part of the semiconductor substrate located between a side surface of the STI region and a side surface of the gate trench; a fourth step of forming a gate insulating film on the side surface of the gate trench; a fifth step of forming a gate electrode, at least a part of the gate electrode being buried in the gate trench; and a sixth step of forming a source region and a drain region in regions located on both sides of the gate trench in an extension direction of the gate trench, respectively, so that the part of the semiconductor substrate functions as a channel region.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Abstract: A first well region of a second conductivity type is formed in the portion of the semiconductor layer of the first conductivity type located in an element portion in which a vertical element is disposed, while a second well region of the second conductivity type is formed in the portion of the semiconductor layer located in a peripheral portion surrounding the element portion. A field insulating film is formed on the portion of the semiconductor layer located in a field portion interposed between the element portion and the peripheral portion. A depletion stop region of the first conductivity type having an impurity concentration higher than that of the semiconductor layer is formed in a surface portion of the semiconductor layer located under at least the portion of the field insulating film adjacent to the peripheral portion.

Abstract: An inverter for driving a motor includes a plurality of power semiconductor devices. The plurality of power semiconductor devices include a resistance electrically connected between a collector and an emitter of an IGBT element. Each of the power semiconductor devices forms any one of a U-phase arm, a V-phase arm and a W-phase arm of the inverter. As a result, a discharge resistance is built in the inverter, and therefore, it is not required to prepare the discharge resistance separately. Thus, the number of components required for a motor drive apparatus can be decreased and the number of operation steps can be reduced.

Abstract: A semiconductor device has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type complementary to the first conductivity type arranged in or on the first semiconductor layer. The semiconductor device has a region of the first conductivity type arranged in the second semiconductor layer. A first electrode contacts the region of the first conductivity type and the second semiconductor layer. A trench extends into the first semiconductor layer, and a voltage dependent short circuit diverter structure has a highly-doped diverter region of the second conductivity type. This diverter region is arranged via an end of a channel region and coupled to a diode arranged in the trench.

Abstract: Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.

Abstract: A power semiconductor component includes a semiconductor body and a field electrode. The semiconductor body has a drift zone of a first conduction type and a further component defining a junction therebetween. The junction is configured to cause a space charge zone to propagate when a reverse voltage is applied to the junction. The field electrode is arranged adjacent to the drift zone, and is insulated from the semiconductor body by at least a dielectric layer. The dielectric layer has a first section and a second section, the first section arranged nearer to the junction and having a higher dielectric constant than the second section.

Abstract: In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence.

Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: Disclosed herein is a semiconductor device including an isolation structure and a recess gate and a method for fabricating the same. The method for fabricating a semiconductor device includes: forming a trench by selectively etching an isolation region of a semiconductor substrate to define an active region; forming a first SOD partially filling the trench; forming a stress shielding layer, which is denser than the first SOD, over the first SOD; forming a second SOD that fills the trench over the first SOD including the stress shielding layer; forming a recess groove by selectively etching a portion of the active region, wherein an upper surface of the first SOD is spaced downwardly from a bottom of the recess groove, and an upper surface of the stress shielding layer is spaced upwardly from the bottom of the recessed groove; and forming a gate of a transistor that fills the recess groove.

Abstract: Embodiments relate to a semiconductor device. In embodiments, a semiconductor device may include a semiconductor substrate having isolation layers and a well region, a gate electrode formed within a trench having a predetermined depth in the well region, source/drain regions formed at both sides of the trench, respectively, an interlayer dielectric layer formed on the semiconductor substrate to have predetermined contact holes, and metal interconnections formed within the contact holes, respectively.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: A semiconductor device is provided which is suitable for a DRAM with word lines and configured to have a trench gate transistor and suppress an increase in the capacitance of a word line without affecting the transistor characteristics. The semiconductor device includes a trench gate transistor which is provided with: a trench which is provided with vertical sides and is formed in a semiconductor substrate; a gate electrode which is formed inside the trench via a gate dielectric film; and a source and a drain which are provided at the semiconductor substrate in the vicinity of the gate electrode via the gate dielectric film, wherein at least one of the thickness of the gate dielectric film in a region contacting the source and the thickness of the gate dielectric film in a region contacting the drain are larger than the thickness of the gate dielectric film formed inside the trench.

Abstract: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction.