Active Layer Is Group Iii-v Compound (epo) Patents (Class 257/E21.393)
  • Patent number: 8252662
    Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
  • Patent number: 8193016
    Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: June 5, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
  • Patent number: 8173469
    Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 8, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Wook Park, Myung Hoon Jung
  • Patent number: 7842595
    Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 30, 2010
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Nick Sauer, Nils Weimann, Liming Zhang
  • Patent number: 7763928
    Abstract: A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: July 27, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Hsien Lin, Wen-Fang Lee, Ya-Huang Huang, Ming-Yen Liu, Yu-Kang Shen
  • Patent number: 7507676
    Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas, and a third process gas containing a carbon hydride gas. This method includes repeatedly performing supply of the first process gas to the process field, supply of the second process gas to the process field, and supply of the third process gas to the process field. The supply of the third process gas includes an excitation period of supplying the third process gas to the process field while exciting the third process gas by an exciting mechanism.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 24, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe