With Multiple Gate, One Gate Having Mos Structure And Others Having Same Or A Different Structure, I.e., Non Mos, E.g., Jfet Gate (epo) Patents (Class 257/E21.421)
  • Patent number: 10700205
    Abstract: A method for forming a semiconductor structure includes receiving a substrate including a dielectric structure; forming a first recess in the substrate; forming a dielectric spacer over a sidewall of the first recess; forming a first semiconductor layer to fill the first recess; removing the dielectric structure to form a second recess over the substrate; and forming a second semiconductor layer to fill the second recess. The dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Patent number: 10573562
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10403550
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
  • Patent number: 10355137
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 10312104
    Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10205022
    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 10157918
    Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10083839
    Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 9991388
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9917240
    Abstract: A thermoelectric element is provided as follows. First and second semiconductor fin structures are disposed on a semiconductor substrate. Each semiconductor fin structure extends in a first direction, protruding from the semiconductor substrate. First and second semiconductor nanowires are disposed on the first and second semiconductor fin structures, respectively. The first semiconductor nanowires include first impurities. The second semiconductor nanowires include second impurities different from the first impurities. A first electrode is connected to first ends of the first and second semiconductor nanowires. A second electrode is connected to second ends of the first semiconductor nanowires. A third electrode is connected to second ends of the second semiconductor nanowires.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Ho Kim, Jun-Hyeok Yang, Hyung-Jong Ko, Se-Ki Kim, Ho-Jin Park, Se-Ra An
  • Patent number: 9842737
    Abstract: Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9704866
    Abstract: In one aspect thereof the invention provides a structure that includes a substrate having a surface and a plurality of fins supported by the surface of the substrate. The plurality of fins are formed of Group IVA-based crystalline semiconductor material and are spaced apart and generally parallel to one another. In the structure at least some of the plurality of fins comprise an amorphous region forming a nanowire precursor structure that is located along a length of the fin where a Group III-V transistor is to be located. A method to fabricate the structure and other structures is also disclosed.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9627245
    Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 18, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Nicolas Loubet
  • Patent number: 9608116
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9461110
    Abstract: An embodiment is a method including forming a fin on a substrate. The fin includes a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. The method further includes converting at least a portion of the first crystalline semiconductor material and second crystalline semiconductor material in the fin to a dielectric material and removing at least a portion of the dielectric material. The method further includes forming a gate structure over the fin and forming source/drain regions on opposing sides of the gate structure.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Chi-Wen Liu, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 9443769
    Abstract: Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 9299842
    Abstract: Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-hoon Baek
  • Patent number: 9269583
    Abstract: Provided is a method for fabricating a memory device, including the following steps. A plurality of semiconductor fin structures is formed on a substrate. Each semiconductor fin structure includes a first doped region and a body region on which the first doped region is disposed, and a trench is disposed between adjacent two semiconductor fin structures. A second doped region is formed in the substrate under the body regions of the semiconductor fin structures and the trenches. A plurality of first contacts are formed on the substrate. A plurality of second contacts are formed on the substrate. Each second contact is electrically connected with the corresponding first doped region.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 23, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shih-Guei Yan, Chih-Chieh Cheng, Wen-Jer Tsai
  • Patent number: 9029923
    Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 12, 2015
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9023704
    Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Young Yoon, Chang-Sun Hwang, Bo-Kyeong Kang, Jae-Seok Kim, Ho-Young Kim, Bo-Un Yoon
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 8999815
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Patent number: 8987792
    Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jaroslaw Adamski, Chris Olson
  • Patent number: 8987093
    Abstract: Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eric C. Harley, Judson Robert Holt, Alexander Reznicek, Thomas N. Adam
  • Patent number: 8975141
    Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Andy C. Wei, Bin Yang, Francis M. Tambwe
  • Patent number: 8946791
    Abstract: A gate dielectric and a gate electrode are formed over a plurality of semiconductor fins. An inner gate spacer is formed and source/drain extension regions are epitaxially formed on physically exposed surface of the semiconductor fins as discrete components that are not merged. An outer gate spacer is subsequently formed. A merged source region and a merged drain region are formed on the source extension regions and the drain extension regions, respectively. The increased lateral spacing between the merged source/drain regions and the gate electrode through the outer gate spacer reduces parasitic capacitance for the fin field effect transistor.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita
  • Patent number: 8928074
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 6, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Lin Cheng, Michael Mazzola
  • Patent number: 8921172
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8916441
    Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
  • Patent number: 8884343
    Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard Lange, Juergen Neuhaeusler
  • Patent number: 8883577
    Abstract: A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yasuo Nara
  • Patent number: 8878275
    Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sunglyong Kim, Mark Schmidt, Christopher Nassar, Steven Leibiger
  • Patent number: 8871584
    Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 28, 2014
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventors: Daniel Tang, Tzu-Shih Yen
  • Patent number: 8866188
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Wann
  • Patent number: 8860140
    Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 14, 2014
    Assignee: Tsinghua University
    Inventors: Renrong Liang, Ning Cui, Jing Wang, Jun Xu
  • Patent number: 8853008
    Abstract: FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally doped region of counter-doped semiconductor is formed on the fin using methods such as monolayer doping, sacrificial oxide doping, or low energy plasma doping. Halo-doped regions are formed by angled ion implantation. The halo-doped regions are disposed in the lower portion of the source and drain and adjacent to the fin. Energy band barrier regions can be formed at the edges of the halo-doped regions by angled ion implantation.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Mankoo Lee
  • Patent number: 8846464
    Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
  • Patent number: 8841728
    Abstract: In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type, a first insulating film and a second insulating film that are provided on the semiconductor layer between the first diffusion layer and the second diffusion layer at a distance, a gate electrode provided on the first insulating film, and a threshold regulating electrode provided on the second insulating film.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Kondo, Akira Hokazono
  • Patent number: 8841182
    Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film including titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that includes titanium and at least one halide ligand, a second source chemical that includes metal and carbon, where the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, where the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. The treatment can form a capping layer on the metal carbide film.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jerry Chen, Vladimir Machkaoutsan, Brennan Milligan, Jan Willem Maes, Suvi Haukka, Eric Shero, Tom E. Blomberg, Dong Li
  • Patent number: 8841188
    Abstract: A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8835233
    Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Bamidele S. Allimi
  • Patent number: 8822290
    Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Meng-Ku Chen, Huicheng Chang
  • Patent number: 8815690
    Abstract: The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 26, 2014
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 8803203
    Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 12, 2014
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8803276
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
  • Patent number: 8785285
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8772099
    Abstract: A method of detecting a detection target using a sensor requires a sensor having a transistor selected from the group of field-effect transistors or single electron transistors. The transistor includes a substrate, a source electrode disposed on the substrate and a drain electrode disposed on the substrate, and a channel forming a current path between the source electrode and the drawing electrode; an interaction-sensing gate comprising a specific substance; and a voltage gate. The method includes (a) providing the detection target on the interaction-sensing gate; (b) setting the gate voltage in the voltage gate at a predetermined level; (c) selectively interacting the specific substance with the detection target; (d) when the detection target interacts with the specific substance, changing a gate voltage in the voltage gate to adjust a characteristic of the transistor; and (e) measuring a change in the characteristic of the transistor to determine a presence of the detection target.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Japan Science and Technology Agency
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8772173
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-kwan Yu, Dong-suk Shin, Pan-kwi Park, Ki-eun Kim
  • Patent number: 8754455
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8748938
    Abstract: There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N+ region and a P region are formed from the bottom. On an upper side surface of this P region, an N region and a P+ region are formed from an inner side of the island-shaped semiconductor. Above the P region, a P+ region is formed. By setting the P+ region and the P+ region to have a low-level voltage and setting the signal line N+ region to have a high-level voltage that is higher than the low-level voltage, signal charges accumulated in the N region are discharged to the signal line N+ region via the P region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: June 10, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada