With Charge Trapping Gate Insulator, E.g., Mnos Transistor (epo) Patents (Class 257/E21.423)
  • Publication number: 20120175697
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 12, 2012
    Inventors: MARK D. HALL, Mehul D. Shroff
  • Patent number: 8217447
    Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: July 10, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Cheon-Man Shim
  • Publication number: 20120168850
    Abstract: A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.
    Type: Application
    Filed: December 2, 2011
    Publication date: July 5, 2012
    Inventors: Ki-Hong LEE, Kwon Hong, Beom-yong Kim
  • Publication number: 20120168848
    Abstract: A non-volatile memory device includes a channel structure extended in a first direction that includes a plurality of inter-layer dielectric layers and a plurality of channel layers alternately stacked over a substrate such that each inter-layer dielectric layer is adjacent to a corresponding one of the plurality of channel layers. A word line extends in a second direction crossing the first direction over the channel structure, and a gate electrode protrudes from the word line in a downward direction to contact a sidewall of the channel structure. A memory gate insulation layer is interposed between the gate electrode and the channel structure, where sidewalls of the channel layers contacting the gate electrode are protruded toward the gate electrode, compared with sidewalls of the inter-layer dielectric layers.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 5, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jung-Ryul AHN
  • Patent number: 8207572
    Abstract: A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Mizushima, Fumihiko Hayashi
  • Publication number: 20120156847
    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: STMicroelectronics Inc.
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
  • Publication number: 20120153377
    Abstract: Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Shenqing FANG, Tung-Sheng CHEN
  • Publication number: 20120146127
    Abstract: A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 14, 2012
    Inventors: Ki-Hong LEE, Kwon HONG, Dae-Gyu SHIN
  • Publication number: 20120146053
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.
    Type: Application
    Filed: September 20, 2011
    Publication date: June 14, 2012
    Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi, Kensuke Ota
  • Publication number: 20120146122
    Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Inventors: Sung Jin WHANG, Ki Hong Lee
  • Patent number: 8198671
    Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 12, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Sean Olsen, Tze Wing Poon, Udayan Ganguly, Johanes Swenberg
  • Patent number: 8193053
    Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Digh Hisamoto, Shin'ichiro Kimura, Daiske Okada, Kan Yasui
  • Patent number: 8193577
    Abstract: A nonvolatile semiconductor memory device includes a source region and a drain region provided apart from each other in a semiconductor substrate, a first insulating film provided on a channel region between the source region and the drain region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer and including a stacked structure of a lanthanum aluminum silicate film and a dielectric film made of silicon oxide or silicon oxynitride, and a control gate electrode provided on the second insulating film.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Takashima, Masao Shingu, Naoki Yasuda, Koichi Muraoka
  • Patent number: 8193055
    Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: June 5, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
  • Publication number: 20120132997
    Abstract: To provide a technology capable of manufacturing a semiconductor device equipped with a HK/MG transistor having a gate insulating film comprised of a high-k material and a gate electrode comprised of a metal material and having stable operation characteristics. A film stack configuring an Nch gate stack structure is formed only in a region located in an active region surrounded with an element isolation portion and in which a gate of a core nMIS is to be formed in a later step is formed, while a film stack configuring a Pch gate stack structure is formed in a region other than the above region. This makes it possible to reduce a supply amount of oxygen atoms to be attracted from the element isolation portion to the region in which the gate of the core nMIS is to be formed.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 31, 2012
    Inventor: Hirofumi TOKITA
  • Publication number: 20120132983
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction.
    Type: Application
    Filed: March 18, 2011
    Publication date: May 31, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Publication number: 20120135593
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KITO, Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Megumi ISHIDUKI, Yosuke KOMORI, Hideaki AOCHI
  • Publication number: 20120135595
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8187938
    Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Yun Lim, Eun-Seok Choi, Young-Wook Lee, Won-Joon Choi, Ki-Hong Lee, Sang-Bum Lee
  • Publication number: 20120126308
    Abstract: A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 24, 2012
    Inventors: Beom Yong KIM, Kwon HONG, Kee Jeung LEE, Ki Hong LEE
  • Publication number: 20120127795
    Abstract: A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 24, 2012
    Applicant: MACRONIX International Co., Ltd
    Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Publication number: 20120126307
    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 24, 2012
    Applicant: MACRONIX International Co., Ltd.
    Inventors: GUAN-WEI WU, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Publication number: 20120122283
    Abstract: A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 17, 2012
    Inventors: Jong-Won LEE, Jae-Seok Kim, Bo-Un Yoon
  • Publication number: 20120119280
    Abstract: A charge trapping non-volatile memory may be made with a charge trapping medium including a pair of dielectric layers sandwiching a metal or semimetal layer. The metal or semimetal layer may exhibit a lower energy level than either of the adjacent sandwiching charge trapping layers, creating a good electron sink and, in some embodiments, resulting in a thinner charge trapping medium.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 17, 2012
    Inventor: Paolo Tessariol
  • Publication number: 20120122285
    Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
    Type: Application
    Filed: January 24, 2012
    Publication date: May 17, 2012
    Inventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
  • Publication number: 20120115294
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 10, 2012
    Inventors: Jong-Won Kim, Woon-Kyung Lee
  • Publication number: 20120115289
    Abstract: Numerous other aspects are provided a method for making a nonvolatile memory cell. The method includes forming a non-planar dielectric structure, and conformally depositing a semiconductor layer over the dielectric structure. A portion of the semiconductor layer serves as a channel region for a transistor, and the channel region is non-planar in shape.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Inventor: Roy E. Scheuerlein
  • Publication number: 20120115293
    Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 10, 2012
    Inventors: Jin-Tae NOH, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
  • Publication number: 20120112265
    Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 10, 2012
    Applicant: GENUSION, INC.
    Inventors: Natsuo AJIKA, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
  • Patent number: 8174068
    Abstract: A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: May 8, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiro Nojima
  • Publication number: 20120104483
    Abstract: A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Inventors: MEHUL D. SHROFF, Mark D. Hall
  • Publication number: 20120098047
    Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Inventors: Rhett T. Brewer, Durai V. Ramaswamy
  • Publication number: 20120100684
    Abstract: A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Young Min, Yu-Gyun Shin, Gab-Jin Nam, Young-Pil Kim
  • Patent number: 8163620
    Abstract: The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: April 24, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yongliang Li, Qiuxia Xu
  • Patent number: 8159018
    Abstract: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: April 17, 2012
    Assignee: NXP B.V.
    Inventors: Nader Akil, Prabhat Agarwal, Robertus T. F. Van Schaijk
  • Patent number: 8154072
    Abstract: A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koike, Yuichiro Mitani, Tatsuo Shimizu, Naoki Yasuda, Yasushi Nakasaki, Akira Nishiyama
  • Publication number: 20120083086
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Inventor: Masatomi OKANISHI
  • Patent number: 8148770
    Abstract: A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: April 3, 2012
    Assignee: Spansion LLC
    Inventors: Shankar Sinha, Timothy Thurgate
  • Patent number: 8148757
    Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Terai, Shinji Fujieda, Akio Toda
  • Publication number: 20120074486
    Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 29, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: HANG-TING LUE, Szu-Yu Wang
  • Publication number: 20120074484
    Abstract: A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 29, 2012
    Inventors: Jin-Kyu KANG, Woon-Kyung LEE, Jee-Yong KIM, Jung-Hwan LEE
  • Patent number: 8143129
    Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: March 27, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Ravindra Kapre, Jeremy Warren
  • Patent number: 8143665
    Abstract: The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: March 27, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou
  • Publication number: 20120070951
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (18) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor.
    Type: Application
    Filed: December 21, 2010
    Publication date: March 22, 2012
    Inventor: Masaya HOSAKA
  • Publication number: 20120068256
    Abstract: An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryo Fukuda, Yoshihisa Iwata
  • Publication number: 20120064681
    Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Inventors: Jingyun Kim, Myoungbum Lee, Kihyun Hwang
  • Publication number: 20120058611
    Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.
    Type: Application
    Filed: November 14, 2011
    Publication date: March 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin T. Voegeli, Kimball M. Watson
  • Patent number: 8129775
    Abstract: The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an amorphous layer disposed adjacent to the gate electrode.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: March 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Koji Akiyama, Hirokazu Higashijima, Tetsushi Ozaki, Tetsuya Shibata
  • Publication number: 20120052673
    Abstract: A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.
    Type: Application
    Filed: August 5, 2011
    Publication date: March 1, 2012
    Inventors: Dong-Chul Yoo, Ki-Hyun Hwang, Han-Mei Choi, Jin-Gyun Kim
  • Publication number: 20120052672
    Abstract: A method for fabricating a cell string includes forming an interlayer dielectric layer, a sacrificial layer, and a semiconductor pattern on a semiconductor substrate, such that the interlayer dielectric layer and the sacrificial layer are formed in a first direction parallel with the semiconductor substrate, and such that the semiconductor pattern is formed in a second direction perpendicular to the semiconductor substrate, forming an opening by patterning the interlayer dielectric layer and the sacrificial layer, filling the opening with a metal, and annealing the semiconductor pattern having the opening filled with the metal.
    Type: Application
    Filed: August 4, 2011
    Publication date: March 1, 2012
    Inventors: Toshiro Nakanishi, Choong-Man Lee