Using Dummy Gate Wherein At Least Part Of Final Gate Is Self-aligned To Dummy Gate (epo) Patents (Class 257/E21.444)
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Publication number: 20120003804Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.Type: ApplicationFiled: September 14, 2011Publication date: January 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
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Patent number: 8071437Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: GrantFiled: November 19, 2009Date of Patent: December 6, 2011Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng
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Publication number: 20110256683Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.Type: ApplicationFiled: June 22, 2010Publication date: October 20, 2011Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Wenwu Wang
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Patent number: 8030196Abstract: A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.Type: GrantFiled: January 12, 2010Date of Patent: October 4, 2011Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Bong-Seok Seo, Jong-Ho Yang, Dong Hee Yu, O Sung Kwon, Oh-Jung Kwon
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Patent number: 8017479Abstract: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region.Type: GrantFiled: April 5, 2010Date of Patent: September 13, 2011Assignee: Hynix Semiconductor Inc.Inventor: Dae Sik Kim
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Patent number: 8013384Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure cType: GrantFiled: September 1, 2009Date of Patent: September 6, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Giuseppe Arena, Giuseppe Ferla, Marco Camalleri
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Patent number: 7994575Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.Type: GrantFiled: July 6, 2005Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Larry Alan Nesbit
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Patent number: 7981735Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: GrantFiled: May 4, 2009Date of Patent: July 19, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yark Yeon Kim, Seong Jae Lee, Moon Gyu Jang, Chel Jong Choi, Myung Sim Jun, Byoung Chul Park
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Patent number: 7968466Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.Type: GrantFiled: November 27, 2007Date of Patent: June 28, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kenji Ishikawa, Hideharu Shido, Takeo Nagata, Teruo Kurahashi, Yasuyoshi Mishima
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Patent number: 7964487Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.Type: GrantFiled: June 4, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Haining S Yang
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Patent number: 7955909Abstract: A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described.Type: GrantFiled: March 28, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Junedong Lee
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Patent number: 7951673Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.Type: GrantFiled: February 26, 2010Date of Patent: May 31, 2011Assignee: Intel CorporationInventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
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Patent number: 7951660Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.Type: GrantFiled: November 7, 2003Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Larry Alan Nesbit
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Patent number: 7939392Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.Type: GrantFiled: June 22, 2009Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang
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Patent number: 7927943Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.Type: GrantFiled: June 22, 2009Date of Patent: April 19, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiung-Han Yeh, Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang
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Patent number: 7923321Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.Type: GrantFiled: June 19, 2009Date of Patent: April 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen
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Patent number: 7919379Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.Type: GrantFiled: September 10, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Eduard A. Cartier, Rashmi Jha, Sivananda Kanakasabapathy, Xi Li, Renee T. Mo, Vijay Narayanan, Vamsi Paruchuri, Mark T. Robson, Kathryn T. Schonenberg, Michelle L. Steen, Richard Wise, Ying Zhang
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Patent number: 7919375Abstract: A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes.Type: GrantFiled: September 16, 2008Date of Patent: April 5, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Dae-Kyeun Kim
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Patent number: 7915105Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.Type: GrantFiled: April 29, 2009Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Shun Wu Lin, Chung-Ming Wang, Chi-Chun Chen
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Patent number: 7898065Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.Type: GrantFiled: December 10, 2009Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7871915Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).Type: GrantFiled: March 26, 2009Date of Patent: January 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Yong-Tian Hou, Chien-Hao Chen, Chi-Chun Chen
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Patent number: 7858481Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.Type: GrantFiled: June 15, 2005Date of Patent: December 28, 2010Assignee: Intel CorporationInventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
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Patent number: 7858457Abstract: Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.Type: GrantFiled: June 2, 2008Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ming Li
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Publication number: 20100311231Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: ApplicationFiled: June 4, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7847339Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.Type: GrantFiled: July 1, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Hyun Lee, Jung-Yun Choi
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Patent number: 7842573Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.Type: GrantFiled: March 4, 2009Date of Patent: November 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. G. Chindalore, Laureen H. Parker
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Patent number: 7838356Abstract: A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved.Type: GrantFiled: December 31, 2008Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Freidoon Mehrad, Shaofeng Yu
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Patent number: 7834407Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: GrantFiled: May 26, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 7820513Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: October 28, 2008Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Rafael Rios, Tom Linton, Suman Datta
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Patent number: 7781316Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.Type: GrantFiled: August 14, 2007Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7772076Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.Type: GrantFiled: March 9, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
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Patent number: 7767535Abstract: A semiconductor device comprising a semiconductor substrate having a recess whose depth is not more than 6 nm, a source region and a drain region which are formed in a surface region of the semiconductor substrate so as to sandwich the recess, each of the source region and the drain region being constituted of an extension region and a contact junction region, a gate insulating film formed between the source region and the drain region in the semiconductor substrate, and a gate electrode formed on the gate insulating film.Type: GrantFiled: October 24, 2005Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kouji Matsuo
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Patent number: 7737506Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Depressions and projections with stripe shape or rectangular shape are formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film along the depressions and projections with stripe shape of the insulating film, or along a longitudinal axis direction or a transverse axis direction of the rectangular shape. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave laser light may also be used.Type: GrantFiled: August 31, 2006Date of Patent: June 15, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi, Mai Akiba
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Patent number: 7723192Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.Type: GrantFiled: March 14, 2008Date of Patent: May 25, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Carter, Michael J. Hargrove, George J. Kluth, John G. Pellerin
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Semiconductor device with current mirror circuit having two transistors of identical characteristics
Patent number: 7723796Abstract: A semiconductor device includes a current-mirror circuit including a first ring-shape gate, a second ring-shape gate, a first diffusion layer formed around the first ring-shape gate and the second ring-shape gate, a second diffusion layer formed inside the first ring-shape gate, a third diffusion layer formed inside the second ring-shape gate, an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential, and an STI area formed around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate constitute the current-mirror circuit, wherein gates of dummy transistors that do not function as transistors are situated between the STI area and the first and second ring-shape gates, and are arranged both in a first direction and in a second direction substantially perpendicular to the first direction.Type: GrantFiled: September 24, 2007Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hiroyoshi Tomita -
Patent number: 7704833Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.Type: GrantFiled: August 25, 2004Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
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Patent number: 7696061Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.Type: GrantFiled: September 26, 2007Date of Patent: April 13, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Ninomiya
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Patent number: 7692275Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.Type: GrantFiled: February 26, 2007Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7674698Abstract: One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.Type: GrantFiled: June 1, 2006Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Paul A. Farrar, Kie Y. Ahn
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Patent number: 7670925Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.Type: GrantFiled: December 17, 2007Date of Patent: March 2, 2010Assignee: Fujitsu LimitedInventors: Hideki Kitada, Takahiro Kimura
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Patent number: 7648898Abstract: A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.Type: GrantFiled: February 19, 2008Date of Patent: January 19, 2010Assignee: DSM Solutions, Inc.Inventor: Srinivasa R. Banna
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Patent number: 7645653Abstract: A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on both the patterned bottom electrode layer and the sacrificial layer pattern, removing the sacrificial layer pattern, and forming a top electrode layer on the exposed bottom electrode layer and the side surface of the sidewall oxide film.Type: GrantFiled: August 24, 2007Date of Patent: January 12, 2010Assignee: Elpida Memory, Inc.Inventor: Yoshihiro Takaishi
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DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR
Publication number: 20090321836Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.Type: ApplicationFiled: May 28, 2009Publication date: December 31, 2009Inventors: Andy Wei, Robert Mulfinger, Thilo Scheiper, Thorsten Kammler -
Patent number: 7625800Abstract: A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region in the substrate; forming a gate spacer on the substrate; forming a channel in the LDD region, forming a gate oxide layer; forming a polysilicon gate electrode; and forming source/drain diffusion regions. Accordingly, a line width of the gate electrode can be reduced without employing lithography of high precision, and an area reserved for salicide can be maximally secured on the gate and source/drain regions.Type: GrantFiled: December 28, 2005Date of Patent: December 1, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Geun Lee
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Patent number: 7601574Abstract: Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.Type: GrantFiled: October 25, 2006Date of Patent: October 13, 2009Assignee: Globalfoundries Inc.Inventor: James Pan
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Patent number: 7592251Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using atomic layer deposition.Type: GrantFiled: December 8, 2005Date of Patent: September 22, 2009Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7575995Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.Type: GrantFiled: December 29, 2005Date of Patent: August 18, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Kim Ki Yong
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Patent number: 7572719Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.Type: GrantFiled: December 2, 2005Date of Patent: August 11, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Kye Nam Lee
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Patent number: 7573108Abstract: A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to a second voltage different than the first voltage. In some embodiments, the difference in voltage between the first voltage and the second voltage is greater than or substantially equal to a difference in voltage between the first voltage and a substrate voltage.Type: GrantFiled: May 12, 2006Date of Patent: August 11, 2009Assignee: Micron Technology, IncInventor: Werner Juengling
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Patent number: 7563637Abstract: Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate electrode may be formed on the semiconductor substrate. The dummy gate may be formed on the field oxide layer. The interlayer dielectric layer may be formed on one side of the dummy gate and includes an opening exposing the photodiode region.Type: GrantFiled: December 22, 2006Date of Patent: July 21, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Young Sik Kim