Multistep Process (epo) Patents (Class 257/E21.46)
  • Patent number: 9705006
    Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuta Endo
  • Patent number: 9006796
    Abstract: A method manufactures a sensor device for sensing a gaseous substance and includes a thin film transistor, which includes a source electrode, a drain electrode and a gate electrode; and an element sensitive to the gaseous substance. In particular, the method includes: forming a first metallic layer on a substrate; defining and patterning the first metallic layer for realizing the gate electrode; depositing a dielectric layer above the gate electrode; depositing a second metallic layer above the layer of dielectric material, defining and patterning the second metallic layer for realizing the source electrode and the drain electrode, and forming the sensitive element by filling a channel region of the thin film transistor with an active layer sensitive to the gaseous substance.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Luigi Giuseppe Occhipinti
  • Patent number: 8969131
    Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Young Ryu, Jin-Won Lee, Woo-Geun Lee, Hee-Jun Byeon, Xun Zhu
  • Patent number: 8946005
    Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Do-Hyun Kim, Eun-Guk Lee, Chang-Oh Jeong
  • Patent number: 8916409
    Abstract: An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Hisham S. Mohamed, Devendra K. Sadana
  • Patent number: 8912544
    Abstract: Provided is a method to manufacture a light-emitting display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kaoru Hatano
  • Patent number: 8877607
    Abstract: To suppress desorption of hydrogen ions with which a single crystal semiconductor substrate is irradiated. A method for manufacturing an SOI substrate includes the following steps: irradiating a semiconductor substrate with carbon ions; irradiating the semiconductor substrate with a hydrogen ion after the irradiation with the carbon ion so as to form an embrittled region in the semiconductor substrate; disposing a surface of the semiconductor substrate and a surface of a base substrate to face each other and to be in contact with each other so that the semiconductor substrate and the base substrate are bonded; and heating the semiconductor substrate and the base substrate which are bonded to each other and separating the semiconductor substrate along the embrittled region so that a semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 8828794
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 8822264
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8772768
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8754420
    Abstract: A semiconductor device of an embodiment includes: a first semiconductor layer made of AlXGa1-XN (0<x<1) or InyAl1-yN (0?y?1); a first semiconductor region, an insulating film, and an anode electrode that are formed on the same plane of the first semiconductor layer, and are made of undoped, n-type, or p-type GaN; and a cathode electrode formed on the first semiconductor region. In this semiconductor device, the first semiconductor region, the insulating film, and the anode electrode are joined to the first semiconductor layer. The insulating film is joined to the first semiconductor layer between the first semiconductor region and the anode electrode. The junction between the anode electrode and the first semiconductor layer is an ohmic junction. The junction between the cathode electrode and the first semiconductor region is an ohmic junction.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Ikeda, Mayumi Morizuka
  • Patent number: 8748878
    Abstract: The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: June 10, 2014
    Assignee: Sony Corporation
    Inventors: Norihiko Yamaguchi, Satoshi Taniguchi, Hiroko Miyashita, Yasuhiro Terai
  • Patent number: 8748223
    Abstract: An object is to provide an oxide semiconductor having stable electric characteristics and a semiconductor device including the oxide semiconductor. A manufacturing method of a semiconductor film by a sputtering method includes the steps of holding a substrate in a treatment chamber which is kept in a reduced-pressure state; heating the substrate at lower than 400° C.; introducing a sputtering gas from which hydrogen and moisture are removed in the state where remaining moisture in the treatment chamber is removed; and forming an oxide semiconductor film over the substrate with use of a metal oxide which is provided in the treatment chamber as a target. When the oxide semiconductor film is formed, remaining moisture in a reaction atmosphere is removed; thus, the concentration of hydrogen and the concentration of hydride in the oxide semiconductor film can be reduced. Thus, the oxide semiconductor film can be stabilized.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Akiharu Miyanaga, Masayuki Sakakura, Junichi Koezuka, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 8698143
    Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara, Tatsuya Takahashi
  • Patent number: 8664653
    Abstract: Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Patent number: 8664036
    Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hotaka Maruyama, Yoshiaki Oikawa, Katsuaki Tochibayashi
  • Patent number: 8647919
    Abstract: Provided is a method to manufacture a light-emitting display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kaoru Hatano
  • Patent number: 8624238
    Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-In Kim, Young-Wook Lee, Jean-Ho Song, Jae-Hyoung Yoon, Sung-Ryul Kim, Byeong-Beom Kim, Je-Hyeong Park, Woo-Geun Lee
  • Patent number: 8617920
    Abstract: It is an object to provide a semiconductor device having excellent electric characteristics or high reliability, or a manufacturing method thereof. A semiconductor device including a gate electrode, an oxide semiconductor layer overlapping with the gate electrode, a source electrode and a drain electrode in contact with the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer is provided. The oxide semiconductor layer is formed by a facing target sputtering method. The carrier concentration of the oxide semiconductor is less than 1×1012/cm3.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8603857
    Abstract: A thin film transistor fabricating method is disclosed. The thin film transistor fabricating method comprises providing a substrate; forming an oxide semiconductor layer on an upper surface of the substrate; forming a gate insulating layer on an upper surface of the oxide semiconductor layer; masking a portion of the oxide semiconductor layer with the gate insulating layer; irradiating the oxide semiconductor layer with irradiating light having photon energy less than a band gap of the oxide semiconductor layer; forming a drain region and a source region at lateral portions of the oxide semiconductor layer exposed to the irradiating light, and forming a channel region in the portion of the oxide semiconductor layer masked by the gate insulating layer; and forming a gate electrode on an upper surface of the gate insulating layer.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 10, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Jian-Shihn Tsang
  • Patent number: 8581244
    Abstract: Example embodiments are directed to oxide thin film transistors and methods of manufacturing the oxide thin film transistors. The oxide thin film transistor includes an active region in a gate insulation layer and under a source and a drain in a bottom gate structure, thus improving electrical characteristics of the oxide thin film transistor.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Seok Park, Tae Sang Kim
  • Patent number: 8557645
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Naoko Kurahashi, Kozo Makiyama
  • Patent number: 8536571
    Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a gate electrode over a substrate; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film; performing heat treatment to form a second oxide semiconductor film after the step of forming the first oxide semiconductor film; forming a first conductive film; forming a first resist mask including regions whose thicknesses are different; etching the second oxide semiconductor film and the first conductive film using the first resist mask to form a third oxide semiconductor film and a second conductive film; reducing the size of the first resist mask to form a second resist mask; selectively etching the second conductive film using the second resist mask to remove a part of the second conductive film so that a source electrode and a drain electrode are formed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8507330
    Abstract: A method is proposed for producing a thin-film transistor (TFT), the method comprising forming a substrate, applying a ZnO-based precursor solution onto the substrate to form a ZnO-based channel layer, annealing the channel layer, forming a source electrode and a drain electrode on the channel layer, forming a dielectric layer on the channel layer and forming a gate electrode on the dielectric layer.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: August 13, 2013
    Assignee: Sony Corporation
    Inventors: Chunmei Wang, Wei Beng Ng, Takehisa Ishida
  • Patent number: 8492756
    Abstract: An object is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. An oxide semiconductor layer including SiOx is used in a channel formation region, and in order to reduce contact resistance with source and drain electrode layers formed using a metal material with low electric resistance, source and drain regions are provided between the source and drain electrode layers and the oxide semiconductor layer including SiOx. The source and drain regions are formed using an oxide semiconductor layer which does not include SiOx or an oxynitride film.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takashi Shimazu, Hiroki Ohara, Toshinari Sasaki, Shunpei Yamazaki
  • Publication number: 20130178013
    Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.
    Type: Application
    Filed: June 27, 2012
    Publication date: July 11, 2013
    Inventors: Pengfei Wang, Chengwei Cao, Qingqing Sun, Wei Zhang
  • Publication number: 20130175505
    Abstract: A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.
    Type: Application
    Filed: August 14, 2012
    Publication date: July 11, 2013
    Inventors: Woo-Yong SUNG, Dong-Hwan KIM, Jeong-Ho LEE, Tae-Woon CHA, Sang-Gun CHOI
  • Patent number: 8470638
    Abstract: A thin film transistor and a manufacturing method thereof are provided. In the manufacturing method of the thin film transistor a semiconductive active layer and a semiconductor passivation layer are sequentially formed such that the semiconductor passivation layer protectively covers the semiconductive active layer. Then the stacked combination of the semiconductive active layer and semiconductor passivation layer are patterned by using a same patterning mask so that formed islands of the semiconductive active layer continue to be protectively covered by formed islands of the semiconductor passivation layer. In one embodiment, the semiconductive active layer is formed of a semiconductive oxide.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong-Kweon Heo, Min-Chul Shin, Chang-Mo Park
  • Patent number: 8450145
    Abstract: A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: May 28, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yushi Inoue
  • Patent number: 8450144
    Abstract: An object of an embodiment of the present invention is to provide a semiconductor device provided with a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor layer including silicon oxide, an insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain regions between the oxide semiconductor layer including silicon oxide and source and drain electrode layers. The source and drain regions are formed using a degenerate oxide semiconductor material or a degenerate oxynitride material.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hideyuki Kishida, Hiroki Ohara, Toshinari Sasaki, Shunpei Yamazaki
  • Publication number: 20130127694
    Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor (TFT) devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. Metal cations are implanted in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The metal cation implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Cheonghong Kim, Tallis Young Chang, John Hyunchul Hong
  • Publication number: 20130119375
    Abstract: Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 16, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130115733
    Abstract: Provided is an etchant composition. The etchant composition according to an exemplary embodiment of the present invention includes ammonium persulfate ((NH4)2)S2O8, an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, and water.
    Type: Application
    Filed: July 12, 2012
    Publication date: May 9, 2013
    Applicants: DONGJIN SEMICHEM CO., LTD, SAMSUNG DISPLAY CO., LTD.
    Inventors: Bong-Kyun KIM, Hong Sick PARK, Wang Woo LEE, Young Woo PARK, Shin Il CHOI, Sang-Woo KIM, Ki-Beom LEE, Dae-Woo LEE, Sam-Young CHO, Jeong-Heon CHOI
  • Publication number: 20130099240
    Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 25, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Hyun-Jung LEE, Sung-Haeng CHO, Woo-Geun LEE, Jang-Hoon HA, Hee-Jun BYEON, Ji-Yun HONG, Ji-Soo OH
  • Patent number: 8426868
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Publication number: 20130078760
    Abstract: A thin film transistor fabricating method is disclosed. The thin film transistor fabricating method comprises providing a substrate; forming an oxide semiconductor layer on an upper surface of the substrate; forming a gate insulating layer on an upper surface of the oxide semiconductor layer; masking a portion of the oxide semiconductor layer with the gate insulating layer; irradiating the oxide semiconductor layer with irradiating light having photon energy less than a band gap of the oxide semiconductor layer; forming a drain region and a source region at lateral portions of the oxide semiconductor layer exposed to the irradiating light, and forming a channel region in the portion of the oxide semiconductor layer masked by the gate insulating layer; and forming a gate electrode on an upper surface of the gate insulating layer.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 28, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: JIAN-SHIHN TSANG
  • Publication number: 20130063675
    Abstract: In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2<S1 within a range in which the oxide semiconductor layer has predetermined electric resistance, and a degree of oxidation S3 of a surface layer portion of the channel region is made higher than the degrees of oxidation S1, S2 of the other regions within the range in which the oxide semiconductor layer has the predetermined electric resistance, by annealing the oxide semiconductor layer in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.
    Type: Application
    Filed: May 24, 2011
    Publication date: March 14, 2013
    Inventor: Katsunori Misaki
  • Patent number: 8395149
    Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: March 12, 2013
    Assignee: Au Optronics Corp.
    Inventors: Yih-Chyun Kao, Chun-Nan Lin, Li-Kai Chen, Wen-Ching Tsai
  • Publication number: 20130048996
    Abstract: Provided a display device including a thin film transistor. The thin film transistor includes a gate electrode, a gate insulating layer which covers the gate electrode, an oxide semiconductor film above the gate insulating layer, a source electrode and a drain electrode which are respectively provided in contact with a first region and a second region, which are provided in the upper surface of the oxide semiconductor film, and a channel protective film which is provided in contact with a third region between the first region and the second region. In plan view, a region of the oxide semiconductor film, which overlaps with the gate electrode, is smaller than the third region, and a portion of the oxide semiconductor film except for a portion which overlaps with the gate electrode has a resistance lower than the portion.
    Type: Application
    Filed: August 28, 2012
    Publication date: February 28, 2013
    Inventors: Takeshi NODA, Tetsufumi Kawamura
  • Publication number: 20130037798
    Abstract: A thin-film transistor with a fluorinated channel and fluorinated source and drain regions and methods of fabrication are provided. The thin-film transistor includes: a substrate; a semiconductor active layer of fluorine-doped metal-oxide formed on the substrate; fluorine-doped source and drain regions disposed adjacent to the semiconductor active layer; a gate electrode disposed over the semiconductor active layer, configured to induce a continuous conduction channel between the source and drain regions; and a gate dielectric material separating the gate electrode and the channel.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 14, 2013
    Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Man WONG, Hoi Sing KWOK, Zhi YE
  • Publication number: 20130037800
    Abstract: A semiconductor device includes an oxide semiconductor film in which a channel portion is formed and a gate portion arranged to be opposed to the channel portion. A drain portion in which the oxide semiconductor film has been subjected to resistance reduction process and an intermediate area which is provided between the drain portion and the channel portion and has not been subjected to resistance reduction process are formed in the oxide semiconductor film, and the semiconductor device includes a conductive film to block resistance reduction process to the intermediate area at least at a part.
    Type: Application
    Filed: January 26, 2011
    Publication date: February 14, 2013
    Inventor: Hiroshi Matsukizono
  • Publication number: 20130017648
    Abstract: Embodiments of the disclosure provide methods of fabricating a thin film transistor device with good profile control of peripheral sidewall of an active layer formed in the thin film transistor devices. In one embodiment, a method for manufacturing a thin film transistor device includes providing a substrate having a source-drain metal electrode layer disposed on an active layer formed thereon, wherein the active layer is a metal oxide layer, performing a back-channel-etching process to form a channel in the source-drain metal electrode layer, and performing an active layer patterning process after the back-channel-etching process.
    Type: Application
    Filed: June 30, 2012
    Publication date: January 17, 2013
    Applicant: Applied Materials, Inc.
    Inventor: Dong-Kil Yim
  • Publication number: 20130001573
    Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: January 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Su LEE, Yoon-Ho KHANG, Se-Hwan YU, Su-Hyoung KANG
  • Publication number: 20120319101
    Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya SASAGAWA, Hiroshi FUJIKI, Yoshinori IEDA
  • Publication number: 20120319113
    Abstract: At least part of the oxide semiconductor layer which serves as the channel formation region is thinned by etching and the thickness of the channel formation region is adjusted by the etching. Further, a dopant containing phosphorus (P) or boron (B) is introduced into a thick region of the oxide semiconductor layer to form a source region and a drain region in the oxide semiconductor layer, so that the contact resistance between the source and drain regions and the channel formation region which are connected to each other is reduced.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20120319102
    Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tatsuya HONDA
  • Publication number: 20120302003
    Abstract: A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.
    Type: Application
    Filed: February 28, 2012
    Publication date: November 29, 2012
    Inventors: Chan-Long Shieh, Gang Yu
  • Publication number: 20120292615
    Abstract: A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Toshihiko Saito
  • Patent number: 8313980
    Abstract: Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto