Manufacture Of Electrodes On Semiconductor Bodies Using Processes Or Apparatus Other Than Epitaxial Growth, E.g., Coating, Diffusion, Or Alloying, Or Radiation Treatment (epo) Patents (Class 257/E21.476)
  • Patent number: 10651173
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guowei Xu, Hui Zang, Ruilong Xie, Haiting Wang
  • Patent number: 10480066
    Abstract: A method of forming conformal amorphous metal films is disclosed. A method of forming crystalline metal films with a predetermined orientation is also disclosed. An amorphous nucleation layer is formed on a substrate surface. An amorphous metal layer is formed from the nucleation layer by atomic substitution. A crystalline metal layer is deposited on the amorphous metal layer by atomic layer deposition.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick
  • Patent number: 10468263
    Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota
  • Patent number: 10147692
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Li-Hsien Huang
  • Patent number: 9911594
    Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
  • Patent number: 9859494
    Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9835788
    Abstract: A light guide film of a mobile device and a mobile device are provided. The light guide film includes a light insulation structure that divides the light guide film into different light guide regions. Each light guide region includes a light inlet configured to receive light from a light source. Different light guide regions correspond to light-transmitting symbols on the mobile device are configured to display different colors.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 5, 2017
    Assignees: Hisense Mobile Communications Technology Co., Ltd., Hisense USA Corp., Hisense International Co., Ltd.
    Inventor: Chengli Ma
  • Patent number: 9515166
    Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: December 6, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
  • Patent number: 9349705
    Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 24, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
  • Patent number: 9012881
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 9006104
    Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Vidmantas Sargunas
  • Patent number: 8993397
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8975118
    Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Julian Gonska, Jens Frey, Heribert Weber, Eckhard Graf, Roman Schlosser
  • Patent number: 8956912
    Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8951445
    Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Javier V. Goicochea, Cyrill Kuemin, Walter H. Riess, Heiko Wolf
  • Patent number: 8941138
    Abstract: A semiconductor structure includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric stacked layer. The oxide channel layer is stacked over the gate, with the gate insulting layer disposed therebetween. The source and the drain are disposed on a side of the oxide channel layer and in parallel to each other. A portion of the oxide channel layer is exposed between the source and the drain. The dielectric stacked layer is disposed on the substrate and includes plural of first inorganic dielectric layers with a first refraction index and plural of second inorganic dielectric layers with a second refraction index that are stacked alternately. At least one of the first inorganic dielectric layers directly covers the source, the drain and the portion of the oxide channel layer. The first refraction index is smaller than the second refraction index.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: January 27, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Tzung-Wei Yu, Fang-An Shu, Yao-Chou Tsai, Kuan-Yi Lin
  • Patent number: 8937013
    Abstract: A method for easily forming a region with conductivity and high wettability without a step for removing a photocatalytic reaction layer, which is formed over a conductive layer, is proposed. The photocatalytic reaction layer is formed over a photocatalytic conductive layer, and the photocatalytic conductive layer is irradiated with ultraviolet light to form a region with conductivity and higher wettability than the photocatalytic reaction layer on a surface of the photocatalytic conductive layer which is irradiated with ultraviolet light. Note that for the photocatalytic conductive layer, a layer having a photocatalytic property of which resistivity is lower than or equal to 1×10?2 ? cm can be used.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masafumi Morisue
  • Patent number: 8928151
    Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Islam Salama, Yonggang Li
  • Patent number: 8900999
    Abstract: A method of filling a feature in a substrate with tungsten without forming a seam is presented. The tungsten is deposited by a thermal chemical vapor deposition (CVD) process using hydrogen (H2) and tungsten hexafluoride (WF6) precursor gases. The H2 to WF6 flow rate ratio is greater than 40 to 1, such as from 40 to 1 to 100 to 1. The substrate temperature during deposition is less than 300 degrees Celsius (° C.) and the processing pressure during deposition is greater than 300 Torr.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kai Wu, Sang-Hyeob Lee, Joshua Collins, Kiejin Park
  • Patent number: 8871565
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 8865534
    Abstract: In a manufacturing process of a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation through heat treatment and oxygen doping treatment are performed. A transistor including an oxide semiconductor film subjected to dehydration or dehydrogenation through heat treatment and oxygen doping treatment can be a highly reliable transistor having stable electric characteristics in which the amount of change in threshold voltage of the transistor between before and after the bias-temperature stress (BT) test can be reduced.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8846459
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield to achieve high productivity. In the manufacture of a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are sequentially stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film, the source electrode layer and the drain electrode layer are formed through an etching step and then a step for removing impurities which are generated by the etching step and exist on a surface of the oxide semiconductor film and in the vicinity thereof is performed.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Satoshi Higano, Shunpei Yamazaki
  • Patent number: 8847365
    Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joseph P. Ellul, Khanh Tran, Edward Martin Godshalk, Albert Bergemont
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8785241
    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hitoshi Nakayama, Masashi Tsubuku, Daigo Shimada
  • Patent number: 8772939
    Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8766263
    Abstract: In an IPS type liquid crystal display device having a reduced number of layers and formed through a reduced number of photolithography steps, an off current of a TFT is prevented from increasing due to photocurrent. A drain line, a TFT drain electrode, and a source electrode each have a multilayer structure including metal and a semiconductor layer. The drain line and the semiconductor layer formed thereunder are separated from the drain electrode and the semiconductor layer formed thereunder with the drain line and the drain electrode connected by a blocking conductive film formed of ITO of which the pixel electrode is also formed. Photocurrent generated by backlight is blocked by the blocking conductive film without flowing into the TFT. Therefore, the number of photomasks required in the production process can be decreased without an increase of causing the off current of the TFT.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 1, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Takahiro Nagami
  • Patent number: 8753910
    Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myong Soo Cho, Ki Yeol Park, Sang Yeob Song, Si Hyuk Lee, Pun Jae Choi
  • Patent number: 8741765
    Abstract: The uniformity of the composition of plated solder bumps from one batch of wafers to another is improved by controlling the rotational speed of the wafers based on the particular solder bump pattern. Embodiments include sequentially horizontal fountain electroplating a pattern of solder bumps, e.g., SnAg solder bumps, on a plurality batches of wafers and controlling the rotational speed of each batch of wafers during electroplating based on a calibration plot of the concentration of a solder bump component, e.g., Ag, as a function of rotational speed for each solder bump pattern, such that the uniformity of the Ag concentration in the patterns of solder bumps is greater than 95%, e.g., greater than 98%. Embodiments further include electroplating in the same plater sequential batches of wafers having both different patterns and different solder bump compositions at the same high throughput.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Christian Schroiff
  • Patent number: 8736028
    Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 8735284
    Abstract: A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kelly Malone, Habib Hichri
  • Patent number: 8728860
    Abstract: Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8722471
    Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 13, 2014
    Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Perrine Batude, Yves Morand
  • Patent number: 8704216
    Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20140098448
    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Brian M. Henderson, Chiew-Guan Tan, Gregory A. Uvieghara, Reza Jalilizeinali
  • Patent number: 8679970
    Abstract: A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac
  • Patent number: 8674351
    Abstract: A data retention period of a memory circuit is lengthened, power consumption is reduced, and a circuit area is reduced. Further, the number of times written data can be read to one data writing operation is increased. A memory circuit has a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of a source and a drain of the third field-effect transistor is electrically connected to a source or a drain of the second field-effect transistor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 8673727
    Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 18, 2014
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Yang-Shun Fan
  • Patent number: 8642462
    Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: February 4, 2014
    Assignee: Micorn Technology, Inc.
    Inventors: Terry Lee Sterrett, Richard J. Harries
  • Patent number: 8633492
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Patent number: 8629062
    Abstract: A method for forming a tungsten film includes forming a tungsten nucleation layer having an amorphous-phase or a ?-phase over a semiconductor substrate. A first tungsten layer having a crystalline ?-phase is then formed over the tungsten nucleation layer to form a low resistivity tungsten film. A second tungsten layer is formed over the first tungsten layer by a physical vapor deposition process, and the second tungsten layer has a large grain size similar to that of the low resistivity tungsten film. The tungsten film has both good surface roughness and low resistivity, thus enhancing the production yield and reliability of a semiconductor device.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ga Young Ha, Jun Ki Kim
  • Patent number: 8618538
    Abstract: A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: December 31, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoon Ho Khang, Se Hwan Yu, Chong Sup Chang, Sang Ho Park, Su-Hyoung Kang
  • Patent number: 8614107
    Abstract: An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
  • Patent number: 8614106
    Abstract: A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
  • Patent number: 8610119
    Abstract: A plasma hydrogenated region in the dielectric layer of a semiconductor thin film transistor (TFT) structure improves the stability of the TFT. The TFT is a multilayer structure including an electrode, a dielectric layer disposed on the electrode, and a metal oxide semiconductor on the dielectric. Exposure of the dielectric layer to a hydrogen containing plasma prior to deposition of the semiconductor produces a plasma hydrogenated region at the semiconductor-dielectric interface. The plasma hydrogenated region incorporates hydrogen which decreases in concentration from semiconductor/dielectric interface into the bulk of one or both of the dielectric layer and the semiconductor layer.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 17, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, David H. Redinger
  • Patent number: 8603918
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Holger Arnim Poehle
  • Patent number: 8603672
    Abstract: A main object of the invention is to provide a cathode active material used to form a lithium secondary battery having the improved cycle characteristics and output. The invention attains the object by providing a semiconductor-covered cathode active material comprising: a cathode active material; and a pn junction semiconductor covering layer which comprises an n-type semiconductor covering layer that covers a surface of the cathode active material and a p-type semiconductor covering layer that covers the surface of the n-type semiconductor covering layer.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: December 10, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hideyuki Koga
  • Patent number: 8597992
    Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Masashi Tsubuku, Hitoshi Nakayama, Daigo Shimada
  • Patent number: 8592297
    Abstract: A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ti Yeh, Wu-Chang Lin, Chung-Yi Huang, Ya Wen Wu, Hui-Mei Jao, Ting-Chun Wang, Chia-Hung Chung
  • Patent number: 8586474
    Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew